| /external/capstone/suite/MC/ARM/ |
| D | neon-vld-encoding.s.cs | 2 0x1f,0x07,0x60,0xf4 = vld1.8 {d16}, [r0:64]
3 0x4f,0x07,0x60,0xf4 = vld1.16 {d16}, [r0]
4 0x8f,0x07,0x60,0xf4 = vld1.32 {d16}, [r0]
5 0xcf,0x07,0x60,0xf4 = vld1.64 {d16}, [r0]
6 0x1f,0x0a,0x60,0xf4 = vld1.8 {d16, d17}, [r0:64]
7 0x6f,0x0a,0x60,0xf4 = vld1.16 {d16, d17}, [r0:128]
8 0x8f,0x0a,0x60,0xf4 = vld1.32 {d16, d17}, [r0]
9 0xcf,0x0a,0x60,0xf4 = vld1.64 {d16, d17}, [r0]
10 0x0f,0x16,0x23,0xf4 = vld1.8 {d1, d2, d3}, [r3]
11 0x5f,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]
[all …]
|
| /external/libavc/common/arm/ |
| D | ih264_inter_pred_luma_bilinear_a9q.s | 136 vld1.8 {q0}, [r0], r3 @// Load row0 ;src1
137 vld1.8 {q2}, [r1], r4 @// Load row0 ;src2
138 vld1.8 {q1}, [r0], r3 @// Load row1 ;src1
140 vld1.8 {q3}, [r1], r4 @// Load row1 ;src2
142 vld1.8 {q4}, [r0], r3 @// Load row2 ;src1
144 vld1.8 {q5}, [r0], r3 @// Load row3 ;src1
146 vld1.8 {q6}, [r1], r4 @// Load row2 ;src2
148 vld1.8 {q7}, [r1], r4 @// Load row3 ;src2
159 vld1.8 {q0}, [r0], r3 @// Load row4 ;src1
161 vld1.8 {q1}, [r0], r3 @// Load row5 ;src1
[all …]
|
| D | ih264_default_weighted_pred_a9q.s | 124 vld1.32 d0[0], [r0], r3 @load row 1 in source 1
125 vld1.32 d0[1], [r0], r3 @load row 2 in source 1
126 vld1.32 d2[0], [r1], r4 @load row 1 in source 2
127 vld1.32 d2[1], [r1], r4 @load row 2 in source 2
129 vld1.32 d1[0], [r0], r3 @load row 3 in source 1
130 vld1.32 d1[1], [r0], r3 @load row 4 in source 1
132 vld1.32 d3[0], [r1], r4 @load row 3 in source 2
133 vld1.32 d3[1], [r1], r4 @load row 4 in source 2
148 vld1.8 d0, [r0], r3 @load row 1 in source 1
149 vld1.8 d4, [r1], r4 @load row 1 in source 2
[all …]
|
| /external/llvm-project/llvm/test/MC/ARM/ |
| D | neon-vld-encoding.s | 3 vld1.8 {d16}, [r0:64]
4 vld1.16 {d16}, [r0]
5 vld1.32 {d16}, [r0]
6 vld1.64 {d16}, [r0]
7 vld1.8 {d16, d17}, [r0:64]
8 vld1.16 {d16, d17}, [r0:128]
9 vld1.32 {d16, d17}, [r0]
10 vld1.64 {d16, d17}, [r0]
11 vld1.8 {d1, d2, d3}, [r3]
12 vld1.16 {d4, d5, d6}, [r3:64]
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | neon-vld-encoding.s | 3 vld1.8 {d16}, [r0:64]
4 vld1.16 {d16}, [r0]
5 vld1.32 {d16}, [r0]
6 vld1.64 {d16}, [r0]
7 vld1.8 {d16, d17}, [r0:64]
8 vld1.16 {d16, d17}, [r0:128]
9 vld1.32 {d16, d17}, [r0]
10 vld1.64 {d16, d17}, [r0]
11 vld1.8 {d1, d2, d3}, [r3]
12 vld1.16 {d4, d5, d6}, [r3:64]
[all …]
|
| /external/llvm-project/llvm/test/Transforms/InstCombine/ARM/ |
| D | vld1.ll | 7 ; Turning a vld1 intrinsic into an llvm load is beneficial
14 ; CHECK-NEXT: [[VLD1:%.*]] = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* [[PTR:%.*]], i32 …
17 %vld1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %ptr, i32 %align)
18 ret <2 x i64> %vld1
24 ; CHECK-NEXT: [[VLD1:%.*]] = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* [[PTR:%.*]], i32 …
27 %vld1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8(i8* %ptr, i32 3)
28 ret <2 x i64> %vld1
37 %vld1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %ptr, i32 1)
38 ret <8 x i8> %vld1
47 %vld1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %ptr, i32 2)
[all …]
|
| /external/libmpeg2/common/arm/ |
| D | impeg2_inter_pred.s | 109 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
113 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
115 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
117 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
119 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
121 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
123 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
125 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
127 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
129 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_mode_18_34.s | 136 vld1.8 {d0},[r8],r6
138 vld1.8 {d1},[r8],r6
140 vld1.8 {d2},[r8],r6
141 vld1.8 {d3},[r8],r6
143 vld1.8 {d4},[r8],r6
144 vld1.8 {d5},[r8],r6
145 vld1.8 {d6},[r8],r6
147 vld1.8 {d7},[r8],r6
167 vld1.8 {d0},[r8],r6
171 vld1.8 {d1},[r8],r6
[all …]
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| D | ihevc_inter_pred_chroma_horz.s | 119 vld1.8 {d0},[r4] @coeff = vld1_s8(pi1_coeff)
166 vld1.u32 {q0},[r12],r11 @vector load pu1_src
168 vld1.u32 {q1},[r12],r11 @vector load pu1_src
170 vld1.u32 {q2},[r12],r11 @vector load pu1_src
172 vld1.u32 {q3},[r12],r9 @vector load pu1_src
176 vld1.u32 {q4},[r4],r11 @vector load pu1_src
178 vld1.u32 {q5},[r4],r11 @vector load pu1_src
180 vld1.u32 {q6},[r4],r11 @vector load pu1_src
182 vld1.u32 {q7},[r4],r9 @vector load pu1_src
223 vld1.u32 {q0},[r12],r11 @vector load pu1_src
[all …]
|
| D | ihevc_intra_pred_luma_mode2.s | 124 vld1.8 {d0},[r0],r8
127 vld1.8 {d1},[r10],r8
130 vld1.8 {d2},[r0],r8
131 vld1.8 {d3},[r10],r8
134 vld1.8 {d4},[r0],r8
135 vld1.8 {d5},[r10],r8
136 vld1.8 {d6},[r0],r8
139 vld1.8 {d7},[r10],r8
180 vld1.8 {d0},[r0],r8
183 vld1.8 {d1},[r10],r8
[all …]
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont-VLD-reencoding.txt | 12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
[all …]
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | neont-VLD-reencoding.txt | 12 # CHECK: vld1.8 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x00]
13 # CHECK: vld1.8 {d0[1]}, [r0], r0 @ encoding: [0xa0,0xf9,0x20,0x00]
14 # CHECK: vld1.8 {d0[2]}, [r0], r0 @ encoding: [0xa0,0xf9,0x40,0x00]
15 # CHECK: vld1.8 {d0[3]}, [r0], r0 @ encoding: [0xa0,0xf9,0x60,0x00]
16 # CHECK: vld1.8 {d0[4]}, [r0], r0 @ encoding: [0xa0,0xf9,0x80,0x00]
17 # CHECK: vld1.8 {d0[5]}, [r0], r0 @ encoding: [0xa0,0xf9,0xa0,0x00]
18 # CHECK: vld1.8 {d0[6]}, [r0], r0 @ encoding: [0xa0,0xf9,0xc0,0x00]
19 # CHECK: vld1.8 {d0[7]}, [r0], r0 @ encoding: [0xa0,0xf9,0xe0,0x00]
30 # CHECK: vld1.16 {d0[0]}, [r0], r0 @ encoding: [0xa0,0xf9,0x00,0x04]
31 # CHECK: vld1.16 {d0[0]}, [r0:16], r0 @ encoding: [0xa0,0xf9,0x10,0x04]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | vld1.ll | 9 ;CHECK: vld1.8 {d16}, [r0:64]
10 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %A, i32 16)
16 ;CHECK: vld1.16
18 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
25 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
28 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
36 ;CHECK: vld1.32
38 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
45 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
48 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vld1.ll | 9 ;CHECK: vld1.8 {d16}, [r0:64]
10 %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %A, i32 16)
16 ;CHECK: vld1.16
18 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
25 ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
28 %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16.p0i8(i8* %tmp0, i32 1)
36 ;CHECK: vld1.32
38 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
45 ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
48 %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8* %tmp0, i32 1)
[all …]
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| /external/libvpx/config/arm-neon/vpx_dsp/arm/ |
| D | vpx_convolve8_avg_horiz_filter_type1_neon.asm.S | 105 vld1.u32 {d0}, [r12], r11 @vector load pu1_src
107 vld1.u32 {d1}, [r12], r11
109 vld1.u32 {d2}, [r12], r11
110 vld1.u32 {d3}, [r12], r11
112 vld1.u32 {d4}, [r12], r11
115 vld1.u32 {d5}, [r12], r11
118 vld1.u32 {d6}, [r12], r11
121 vld1.u32 {d7}, [r12], r11
124 vld1.u32 {d12}, [r4], r11 @vector load pu1_src + src_strd
127 vld1.u32 {d13}, [r4], r11
[all …]
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| D | vpx_convolve8_avg_horiz_filter_type2_neon.asm.S | 106 vld1.u32 {d0}, [r12], r11 @vector load pu1_src
108 vld1.u32 {d1}, [r12], r11
110 vld1.u32 {d2}, [r12], r11
111 vld1.u32 {d3}, [r12], r11
113 vld1.u32 {d4}, [r12], r11
116 vld1.u32 {d5}, [r12], r11
119 vld1.u32 {d6}, [r12], r11
122 vld1.u32 {d7}, [r12], r11
125 vld1.u32 {d12}, [r4], r11 @vector load pu1_src + src_strd
128 vld1.u32 {d13}, [r4], r11
[all …]
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| D | vpx_convolve_avg_neon_asm.asm.S | 42 vld1.8 {q0-q1}, [r0]!
43 vld1.8 {q2-q3}, [r0], lr
45 vld1.8 {q8-q9}, [r6,:128]!
46 vld1.8 {q10-q11}, [r6,:128], r4
58 vld1.8 {q0-q1}, [r0], r1
59 vld1.8 {q2-q3}, [r0], r1
60 vld1.8 {q8-q9}, [r6,:128], r3
61 vld1.8 {q10-q11}, [r6,:128], r3
77 vld1.8 {q0}, [r0], r1
78 vld1.8 {q1}, [r0], r1
[all …]
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| D | vpx_convolve8_horiz_filter_type2_neon.asm.S | 105 vld1.u32 {d0}, [r12], r11 @vector load pu1_src
107 vld1.u32 {d1}, [r12], r11
109 vld1.u32 {d2}, [r12], r11
110 vld1.u32 {d3}, [r12], r11
112 vld1.u32 {d4}, [r12], r11
115 vld1.u32 {d5}, [r12], r11
118 vld1.u32 {d6}, [r12], r11
121 vld1.u32 {d7}, [r12], r11
124 vld1.u32 {d12}, [r4], r11 @vector load pu1_src + src_strd
127 vld1.u32 {d13}, [r4], r11
[all …]
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| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | vpx_convolve8_avg_horiz_filter_type2_neon.asm | 100 vld1.u32 {d0}, [r12], r11 ;vector load pu1_src
102 vld1.u32 {d1}, [r12], r11
104 vld1.u32 {d2}, [r12], r11
105 vld1.u32 {d3}, [r12], r11
107 vld1.u32 {d4}, [r12], r11
110 vld1.u32 {d5}, [r12], r11
113 vld1.u32 {d6}, [r12], r11
116 vld1.u32 {d7}, [r12], r11
119 vld1.u32 {d12}, [r4], r11 ;vector load pu1_src + src_strd
122 vld1.u32 {d13}, [r4], r11
[all …]
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| D | vpx_convolve8_avg_horiz_filter_type1_neon.asm | 99 vld1.u32 {d0}, [r12], r11 ;vector load pu1_src
101 vld1.u32 {d1}, [r12], r11
103 vld1.u32 {d2}, [r12], r11
104 vld1.u32 {d3}, [r12], r11
106 vld1.u32 {d4}, [r12], r11
109 vld1.u32 {d5}, [r12], r11
112 vld1.u32 {d6}, [r12], r11
115 vld1.u32 {d7}, [r12], r11
118 vld1.u32 {d12}, [r4], r11 ;vector load pu1_src + src_strd
121 vld1.u32 {d13}, [r4], r11
[all …]
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| D | vpx_convolve_avg_neon_asm.asm | 36 vld1.8 {q0-q1}, [r0]!
37 vld1.8 {q2-q3}, [r0], lr
39 vld1.8 {q8-q9}, [r6@128]!
40 vld1.8 {q10-q11}, [r6@128], r4
52 vld1.8 {q0-q1}, [r0], r1
53 vld1.8 {q2-q3}, [r0], r1
54 vld1.8 {q8-q9}, [r6@128], r3
55 vld1.8 {q10-q11}, [r6@128], r3
71 vld1.8 {q0}, [r0], r1
72 vld1.8 {q1}, [r0], r1
[all …]
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| D | vpx_convolve8_horiz_filter_type2_neon.asm | 99 vld1.u32 {d0}, [r12], r11 ;vector load pu1_src
101 vld1.u32 {d1}, [r12], r11
103 vld1.u32 {d2}, [r12], r11
104 vld1.u32 {d3}, [r12], r11
106 vld1.u32 {d4}, [r12], r11
109 vld1.u32 {d5}, [r12], r11
112 vld1.u32 {d6}, [r12], r11
115 vld1.u32 {d7}, [r12], r11
118 vld1.u32 {d12}, [r4], r11 ;vector load pu1_src + src_strd
121 vld1.u32 {d13}, [r4], r11
[all …]
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| D | vpx_convolve8_horiz_filter_type1_neon.asm | 99 vld1.u32 {d0}, [r12], r11 ;vector load pu1_src
101 vld1.u32 {d1}, [r12], r11
103 vld1.u32 {d2}, [r12], r11
104 vld1.u32 {d3}, [r12], r11
106 vld1.u32 {d4}, [r12], r11
109 vld1.u32 {d5}, [r12], r11
112 vld1.u32 {d6}, [r12], r11
115 vld1.u32 {d7}, [r12], r11
118 vld1.u32 {d12}, [r4], r11 ;vector load pu1_src + src_strd
121 vld1.u32 {d13}, [r4], r11
[all …]
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_esbr_cos_sin_mod_loop1.s | 40 vld1.32 {d0} , [r2]!
42 vld1.32 {d2[0]}, [r0]!
44 vld1.32 {d2[1]}, [r7]
45 vld1.32 {d3[0]}, [r4]
47 vld1.32 {d3[1]}, [r7]
66 vld1.32 {d0} , [r2]!
68 vld1.32 {d2[0]}, [r0]!
70 vld1.32 {d2[1]}, [r7]
71 vld1.32 {d3[0]}, [r4]
73 vld1.32 {d3[1]}, [r7]
[all …]
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| /external/libavc/encoder/arm/ |
| D | ime_distortion_metrics_a9q.s | 98 vld1.8 {d4, d5}, [r0], r2
99 vld1.8 {d6, d7}, [r1], r3
101 vld1.8 {d8, d9}, [r0], r2
104 vld1.8 {d10, d11}, [r1], r3
108 vld1.8 {d4, d5}, [r0], r2
111 vld1.8 {d6, d7}, [r1], r3
113 vld1.8 {d8, d9}, [r0], r2
116 vld1.8 {d10, d11}, [r1], r3
180 vld1.8 {d4, d5}, [r0], r2
181 vld1.8 {d6, d7}, [r1], r3
[all …]
|