| /external/llvm-project/llvm/test/MC/ARM/ |
| D | vstrldr_sys.s | 70 vldr fpscr, [r0] label
78 vldr fpscr_nzcvqc, [r9, #-24] label
86 vldr fpscr_nzcvqc, [r9, #-24]! label
94 vldr fpscr_nzcvqc, [r9], #-24 label
102 vldr fpscr_nzcvqc, [sp], #-52 label
156 vldr fpcxts, [r12, #508] label
164 vldr fpcxts, [r12, #508]! label
172 vldr fpcxts, [r12], #508 label
180 vldr fpcxts, [sp], #-24 label
236 vldr fpcxtns, [r0] label
[all …]
|
| D | simple-fp-encoding.s | 240 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
241 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
242 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
244 vldr.64 d17, [r0]
245 vldr.i32 s0, [lr]
246 vldr.d d0, [lr]
248 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
249 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
250 vldr.64 d1, [r2, #32]
251 vldr.f64 d1, [r2, #-32]
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | fp16-fusedMAC.ll | 10 ; CHECK-NEXT: vldr.16 s0, [r1]
11 ; CHECK-NEXT: vldr.16 s2, [r0]
12 ; CHECK-NEXT: vldr.16 s4, [r2]
19 ; DONT-FUSE-NEXT: vldr.16 s0, [r1]
20 ; DONT-FUSE-NEXT: vldr.16 s2, [r0]
22 ; DONT-FUSE-NEXT: vldr.16 s2, [r2]
39 ; CHECK-NEXT: vldr.16 s0, [r2]
40 ; CHECK-NEXT: vldr.16 s2, [r1]
41 ; CHECK-NEXT: vldr.16 s4, [r0]
48 ; DONT-FUSE-NEXT: vldr.16 s0, [r2]
[all …]
|
| D | vsel-fp16.ll | 9 ; CHECK-NEXT: vldr.16 s0, [r2]
10 ; CHECK-NEXT: vldr.16 s2, [r3]
28 ; CHECK-NEXT: vldr.16 s0, [r2]
29 ; CHECK-NEXT: vldr.16 s2, [r3]
47 ; CHECK-NEXT: vldr.16 s0, [r2]
48 ; CHECK-NEXT: vldr.16 s2, [r3]
66 ; CHECK-NEXT: vldr.16 s0, [r2]
67 ; CHECK-NEXT: vldr.16 s2, [r3]
85 ; CHECK-NEXT: vldr.16 s0, [r2]
86 ; CHECK-NEXT: vldr.16 s2, [r3]
[all …]
|
| D | saxpy10-a9.ll | 12 ; CHECK: vldr
13 ; CHECK: vldr
14 ; CHECK: vldr
15 ; CHECK: vldr
16 ; CHECK: vldr
17 ; CHECK-NEXT: vldr
21 ; CHECK-NEXT: vldr
22 ; CHECK-NEXT: vldr
26 ; CHECK-NEXT: vldr
29 ; CHECK-NEXT: vldr
[all …]
|
| D | constantfp.ll | 45 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
48 ; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
53 ; CHECK-XO-FLOAT-NOT: vldr
62 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
65 ; CHECK-NO-XO: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
70 ; CHECK-XO-FLOAT-NOT: vldr
89 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
92 ; CHECK-NO-XO: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
97 ; CHECK-XO-DOUBLE-NOT: vldr
102 ; CHECK-XO-DOUBLE-NOT: vldr
[all …]
|
| D | fp16-fullfp16.ll | 6 ; CHECK: vldr.16 s0, [r1]
7 ; CHECK-NEXT: vldr.16 s2, [r0]
20 ; CHECK: vldr.16 s0, [r1]
21 ; CHECK-NEXT: vldr.16 s2, [r0]
34 ; CHECK: vldr.16 s0, [r1]
35 ; CHECK-NEXT: vldr.16 s2, [r0]
48 ; CHECK: vldr.16 s0, [r1]
49 ; CHECK-NEXT: vldr.16 s2, [r0]
64 ; CHECK-NEXT: vldr.16 s0, [r0]
65 ; CHECK-NEXT: vldr.16 s2, [r1]
[all …]
|
| D | vcgt.ll | 8 ; ALLOC-NEXT: vldr d16, [r1]
9 ; ALLOC-NEXT: vldr d17, [r0]
16 ; BASIC-NEXT: vldr d17, [r1]
17 ; BASIC-NEXT: vldr d16, [r0]
31 ; ALLOC-NEXT: vldr d16, [r1]
32 ; ALLOC-NEXT: vldr d17, [r0]
39 ; BASIC-NEXT: vldr d17, [r1]
40 ; BASIC-NEXT: vldr d16, [r0]
54 ; ALLOC-NEXT: vldr d16, [r1]
55 ; ALLOC-NEXT: vldr d17, [r0]
[all …]
|
| D | vcombine.ll | 6 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
22 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
39 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
56 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
72 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
[all …]
|
| D | vbits.ll | 7 ; CHECK-NEXT: vldr d16, [r1]
8 ; CHECK-NEXT: vldr d17, [r0]
21 ; CHECK-NEXT: vldr d16, [r1]
22 ; CHECK-NEXT: vldr d17, [r0]
35 ; CHECK-NEXT: vldr d16, [r1]
36 ; CHECK-NEXT: vldr d17, [r0]
49 ; CHECK-NEXT: vldr d16, [r1]
50 ; CHECK-NEXT: vldr d17, [r0]
123 ; CHECK-NEXT: vldr d16, [r1]
124 ; CHECK-NEXT: vldr d17, [r0]
[all …]
|
| D | fp16-vminmaxnm.ll | 173 ; CHECK: vldr.16 s2, .LCPI{{.*}}
186 ; CHECK: vldr.16 s2, .LCPI{{.*}}
189 ; CHECK: vldr.16 s2, .LCPI{{.*}}
205 ; CHECK: vldr.16 s2, .LCPI{{.*}}
218 ; CHECK: vldr.16 s2, .LCPI{{.*}}
221 ; CHECK: vldr.16 s2, .LCPI{{.*}}
234 ; CHECK: vldr.16 s2, .LCPI{{.*}}
237 ; CHECK: vldr.16 s2, .LCPI{{.*}}
253 ; CHECK: vldr.16 s2, .LCPI{{.*}}
266 ; CHECK: vldr.16 s2, .LCPI{{.*}}
[all …]
|
| D | neon_ld1.ll | 4 ; CHECK: vldr d
5 ; CHECK: vldr d
19 ; CHECK: vldr d
20 ; CHECK: vldr d
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | vstrldr_sys.txt | 53 # CHECK-NOSEC: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
54 # CHECK-NOMVE: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
55 # CHECK-NOVFP: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
56 # CHECK: vldr fpscr, [r0] @ encoding: [0x90,0xed,0x80,0x2f]
59 # CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
60 # CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
61 # CHECK-NOVFP: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
62 # CHECK: vldr fpscr_nzcvqc, [r9, #-24] @ encoding: [0x19,0xed,0x86,0x4f]
65 # CHECK-NOSEC: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
66 # CHECK-NOMVE: vldr fpscr_nzcvqc, [r9, #-24]! @ encoding: [0x39,0xed,0x86,0x4f]
[all …]
|
| /external/llvm-project/libc/AOR_v20.02/string/arm/ |
| D | memcpy.S | 88 vldr \vreg, [src, #\base]
90 vldr d0, [src, #\base + 8] define
92 vldr d1, [src, #\base + 16] define
94 vldr d2, [src, #\base + 24] define
96 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
98 vldr d0, [src, #\base + 40] define
100 vldr d1, [src, #\base + 48] define
102 vldr d2, [src, #\base + 56] define
107 vldr \vreg, [src, #\base]
109 vldr d0, [src, #\base + 8] define
[all …]
|
| /external/arm-optimized-routines/string/arm/ |
| D | memcpy.S | 87 vldr \vreg, [src, #\base]
89 vldr d0, [src, #\base + 8] define
91 vldr d1, [src, #\base + 16] define
93 vldr d2, [src, #\base + 24] define
95 vldr \vreg, [src, #\base + prefetch_lines * 64 - 32]
97 vldr d0, [src, #\base + 40] define
99 vldr d1, [src, #\base + 48] define
101 vldr d2, [src, #\base + 56] define
106 vldr \vreg, [src, #\base]
108 vldr d0, [src, #\base + 8] define
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | saxpy10-a9.ll | 12 ; CHECK: vldr
13 ; CHECK: vldr
14 ; CHECK: vldr
15 ; CHECK: vldr
16 ; CHECK: vldr
17 ; CHECK-NEXT: vldr
21 ; CHECK-NEXT: vldr
22 ; CHECK-NEXT: vldr
26 ; CHECK-NEXT: vldr
29 ; CHECK-NEXT: vldr
[all …]
|
| D | constantfp.ll | 18 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
27 ; CHECK-NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}}
46 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
55 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
63 ; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
66 ; CHECK-NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}}
|
| D | vcombine.ll | 6 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
7 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
22 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
23 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
39 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
40 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
56 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
57 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
72 ; CHECK-DAG: vldr [[LD0:d[0-9]+]], [r0]
73 ; CHECK-DAG: vldr [[LD1:d[0-9]+]], [r1]
|
| D | vbsl-constant.ll | 5 ;CHECK: vldr
6 ;CHECK: vldr
19 ;CHECK: vldr
20 ;CHECK: vldr
33 ;CHECK: vldr
34 ;CHECK: vldr
47 ;CHECK: vldr
48 ;CHECK: vldr
49 ;CHECK: vldr
|
| D | neon_ld1.ll | 4 ; CHECK: vldr d
5 ; CHECK: vldr d
19 ; CHECK: vldr d
20 ; CHECK: vldr d
|
| /external/capstone/suite/MC/ARM/ |
| D | simple-fp-encoding.s.cs | 89 0x00,0x1b,0xd0,0xed = vldr d17, [r0]
90 0x00,0x0a,0x9e,0xed = vldr s0, [lr]
91 0x00,0x0b,0x9e,0xed = vldr d0, [lr]
92 0x08,0x1b,0x92,0xed = vldr d1, [r2, #32]
93 0x08,0x1b,0x12,0xed = vldr d1, [r2, #-32]
94 0x00,0x2b,0x93,0xed = vldr d2, [r3]
95 0x00,0x3b,0x9f,0xed = vldr d3, [pc]
96 0x00,0x3b,0x9f,0xed = vldr d3, [pc]
97 0x00,0x3b,0x1f,0xed = vldr d3, [pc, #-0]
98 0x00,0x6a,0xd0,0xed = vldr s13, [r0]
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 228 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
229 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
230 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
232 vldr.64 d17, [r0]
233 vldr.i32 s0, [lr]
234 vldr.d d0, [lr]
236 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
237 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
238 vldr.64 d1, [r2, #32]
239 vldr.f64 d1, [r2, #-32]
[all …]
|
| /external/llvm-project/llvm/test/Analysis/CostModel/ARM/ |
| D | add-cast-vect.ll | 34 ; ASM: vldr
36 ; ASM: vldr
51 ; ASM: vldr
53 ; ASM: vldr
68 ; ASM: vldr
70 ; ASM: vldr
85 ; ASM: vldr
87 ; ASM: vldr
|
| /external/llvm/test/Transforms/LoopVectorize/ARM/ |
| D | mul-cast-vect.ll | 34 ; ASM: vldr
36 ; ASM: vldr
51 ; ASM: vldr
53 ; ASM: vldr
68 ; ASM: vldr
70 ; ASM: vldr
85 ; ASM: vldr
87 ; ASM: vldr
|
| /external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
| D | vldr.ll | 13 …%1 = tail call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %0…
20 declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32)
31 …%1 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> …
38 declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32)
53 …%3 = tail call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v…
62 declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1(<2 x…
|