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Searched refs:vmulh (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvmulhq.ll7 ; CHECK-NEXT: vmulh.u8 q0, q0, q1
10 %0 = tail call <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1)
14 declare <16 x i8> @llvm.arm.mve.vmulh.v16i8(<16 x i8>, <16 x i8>, i32) #1
19 ; CHECK-NEXT: vmulh.s16 q0, q0, q1
22 %0 = tail call <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)
26 declare <8 x i16> @llvm.arm.mve.vmulh.v8i16(<8 x i16>, <8 x i16>, i32) #1
31 ; CHECK-NEXT: vmulh.u32 q0, q0, q1
34 %0 = tail call <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1)
38 declare <4 x i32> @llvm.arm.mve.vmulh.v4i32(<4 x i32>, <4 x i32>, i32) #1
/external/llvm-project/llvm/test/MC/ARM/
Dmve-qdest-qsrc.s237 # CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
238 # CHECK-NOFP: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
239 vmulh.s8 q0, q4, q5
241 # CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
242 # CHECK-NOFP: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
243 vmulh.s16 q0, q7, q4
245 # CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
246 # CHECK-NOFP: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
247 vmulh.s32 q0, q7, q4
249 # CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
[all …]
/external/llvm-project/llvm/test/MC/RISCV/rvv/
Dmul.s35 vmulh.vv v8, v4, v20, v0.t
36 # CHECK-INST: vmulh.vv v8, v4, v20, v0.t
41 vmulh.vv v8, v4, v20
42 # CHECK-INST: vmulh.vv v8, v4, v20
47 vmulh.vx v8, v4, a0, v0.t
48 # CHECK-INST: vmulh.vx v8, v4, a0, v0.t
53 vmulh.vx v8, v4, a0
54 # CHECK-INST: vmulh.vx v8, v4, a0
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-qdest-qsrc.txt173 # CHECK: vmulh.s8 q0, q4, q5 @ encoding: [0x09,0xee,0x0b,0x0e]
177 # CHECK: vmulh.s16 q0, q7, q4 @ encoding: [0x1f,0xee,0x09,0x0e]
181 # CHECK: vmulh.s32 q0, q7, q4 @ encoding: [0x2f,0xee,0x09,0x0e]
185 # CHECK: vmulh.u8 q3, q5, q2 @ encoding: [0x0b,0xfe,0x05,0x6e]
189 # CHECK: vmulh.u16 q2, q7, q4 @ encoding: [0x1f,0xfe,0x09,0x4e]
193 # CHECK: vmulh.u32 q1, q3, q2 @ encoding: [0x27,0xfe,0x05,0x2e]
/external/llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
Dunpredload.ll14 ; CHECK-NEXT: vmulh.s16 q2, q1, q1
15 ; CHECK-NEXT: vmulh.s16 q0, q0, q0
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.h542 void vmulh(Type ElmtTy, const Operand *OpQd, const Operand *OpQn,
DIceInstARM32.cpp1214 Asm->vmulh(typeElementType(SrcTy), Dest, getSrc(0), getSrc(1), Unsigned); in emitIAS()
1218 Asm->vmulh(typeElementType(SrcTy), Dest, getSrc(0), getSrc(1), Unsigned); in emitIAS()
DIceAssemblerARM32.cpp3338 void AssemblerARM32::vmulh(Type ElmtTy, const Operand *OpQd, in vmulh() function in Ice::ARM32::AssemblerARM32
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td4169 defm MVE_VMULHs8 : MVE_VMULT<"vmulh", MVE_v16s8, 0b0>;
4170 defm MVE_VMULHs16 : MVE_VMULT<"vmulh", MVE_v8s16, 0b0>;
4171 defm MVE_VMULHs32 : MVE_VMULT<"vmulh", MVE_v4s32, 0b0>;
4172 defm MVE_VMULHu8 : MVE_VMULT<"vmulh", MVE_v16u8, 0b0>;
4173 defm MVE_VMULHu16 : MVE_VMULT<"vmulh", MVE_v8u16, 0b0>;
4174 defm MVE_VMULHu32 : MVE_VMULT<"vmulh", MVE_v4u32, 0b0>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrMVE.td4746 defm MVE_VMULHs8 : MVE_VMULT<"vmulh", MVE_v16s8, 0b0>;
4747 defm MVE_VMULHs16 : MVE_VMULT<"vmulh", MVE_v8s16, 0b0>;
4748 defm MVE_VMULHs32 : MVE_VMULT<"vmulh", MVE_v4s32, 0b0>;
4749 defm MVE_VMULHu8 : MVE_VMULT<"vmulh", MVE_v16u8, 0b0>;
4750 defm MVE_VMULHu16 : MVE_VMULT<"vmulh", MVE_v8u16, 0b0>;
4751 defm MVE_VMULHu32 : MVE_VMULT<"vmulh", MVE_v4u32, 0b0>;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoV.td668 defm VMULH_V : VALU_MV_V_X<"vmulh", 0b100111>;
/external/llvm-project/clang/include/clang/Basic/
Darm_mve.td93 (IRInt<"vmulh", [Vector]> $a, $b, (unsignedflag Scalar))>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc9936 "movnb\006vmovnt\005vmovx\004vmrs\004vmsr\004vmul\005vmulh\005vmull\006v"
13428 …{ 2845 /* vmulh */, ARM::MVE_VMULHs16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEI…
13429 …{ 2845 /* vmulh */, ARM::MVE_VMULHs32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEI…
13430 …{ 2845 /* vmulh */, ARM::MVE_VMULHs8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEIn…
13431 …{ 2845 /* vmulh */, ARM::MVE_VMULHu16, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEI…
13432 …{ 2845 /* vmulh */, ARM::MVE_VMULHu32, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEI…
13433 …{ 2845 /* vmulh */, ARM::MVE_VMULHu8, Convert__Reg1_2__Reg1_3__Reg1_4__VPTPredR3_0, AMFBS_HasMVEIn…
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc1648 "llvm.arm.mve.vmulh",
11781 1, // llvm.arm.mve.vmulh