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Searched refs:vnegd (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s886 # CHECK-BE: vnegd 2, 3 # encoding: [0x10,0x47,0x1e,0x02]
887 # CHECK-LE: vnegd 2, 3 # encoding: [0x02,0x1e,0x47,0x10]
888 vnegd 2, 3
/external/llvm/test/MC/PowerPC/
Dppc64-encoding-vmx.s877 # CHECK-BE: vnegd 2, 3 # encoding: [0x10,0x47,0x1e,0x02]
878 # CHECK-LE: vnegd 2, 3 # encoding: [0x02,0x1e,0x47,0x10]
879 vnegd 2, 3
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dmul-const-vector.ll325 ; CHECK-P9-NEXT: vnegd v[[REG4:[0-9]+]], v[[REG3]]
341 ; CHECK-P9-NEXT: vnegd v{{[0-9]+}}, v[[REG4]]
Dvsx-p9.ll408 ; CHECK: vnegd 2, 2
Dppc64-P9-vabsd.ll105 ; CHECK: vnegd
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DREADME_P9.txt92 - Vector Integer Negate: vnegw vnegd
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
DPPCInstrAltivec.td1457 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
/external/llvm/lib/Target/PowerPC/
DREADME_P9.txt92 - Vector Integer Negate: vnegw vnegd
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
Dp9-instrs.txt419 [PO VRT EO VRB XO] vnegd vnegw
DPPCInstrAltivec.td1305 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
/external/llvm-project/llvm/lib/Target/PowerPC/
DREADME_P9.txt92 - Vector Integer Negate: vnegw vnegd
95 (set v2i64:$rT, (ineg v2i64:$rA)) // vnegd
DPPCInstrAltivec.td1493 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd",
/external/llvm-project/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt796 # CHECK: vnegd 2, 3
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding-vmx.txt793 # CHECK: vnegd 2, 3
/external/swiftshader/third_party/subzero/src/DartARM32/
Dassembler_arm.h745 void vnegd(DRegister dd, DRegister dm, Condition cond = AL);
Dassembler_arm.cc1012 void Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) { in vnegd() function in dart::Assembler
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5600 def vnegd : PatFrag<(ops node:$in),
5608 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5642 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5643 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5644 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td6044 def vnegd : PatFrag<(ops node:$in),
6052 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
6087 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
6088 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
6089 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td6042 def vnegd : PatFrag<(ops node:$in),
6050 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
6085 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
6086 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
6087 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenAsmMatcher.inc4378 "\014vncipherlast\005vnegd\005vnegw\010vnmsubfp\004vnor\004vnot\003vor\004"
6679 …{ 11644 /* vnegd */, PPC::VNEGD, Convert__RegVRRC1_0__RegVRRC1_1, AMFBS_None, { MCK_RegVRRC, MCK_R…