| /external/llvm-project/llvm/test/MC/ARM/ |
| D | neont2-add-encoding.s | 133 @ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xff,0xa2,0x04]
134 vraddhn.i16 d16, q8, q9
135 @ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xff,0xa2,0x04]
136 vraddhn.i32 d16, q8, q9
137 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xff,0xa2,0x04]
138 vraddhn.i64 d16, q8, q9
|
| D | neon-add-encoding.s | 229 @ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf3]
230 vraddhn.i16 d16, q8, q9
231 @ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf3]
232 vraddhn.i32 d16, q8, q9
233 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3]
234 vraddhn.i64 d16, q8, q9
|
| /external/llvm/test/MC/ARM/ |
| D | neont2-add-encoding.s | 133 @ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xff,0xa2,0x04]
134 vraddhn.i16 d16, q8, q9
135 @ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xff,0xa2,0x04]
136 vraddhn.i32 d16, q8, q9
137 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xff,0xa2,0x04]
138 vraddhn.i64 d16, q8, q9
|
| D | neon-add-encoding.s | 229 @ CHECK: vraddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf3]
230 vraddhn.i16 d16, q8, q9
231 @ CHECK: vraddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf3]
232 vraddhn.i32 d16, q8, q9
233 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3]
234 vraddhn.i64 d16, q8, q9
|
| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | vadd.ll | 95 ;CHECK: vraddhn.i16
98 %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
104 ;CHECK: vraddhn.i32
107 %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
113 ;CHECK: vraddhn.i64
116 %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
122 declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vadd.ll | 95 ;CHECK: vraddhn.i16
98 %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
104 ;CHECK: vraddhn.i32
107 %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
113 ;CHECK: vraddhn.i64
116 %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
122 declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
|
| /external/libmpeg2/common/arm/ |
| D | impeg2_idct.s | 233 vraddhn.s32 d12, q0, q4
234 vraddhn.s32 d13, q0, q5
243 vraddhn.s32 d12, q0, q4
244 vraddhn.s32 d13, q0, q5
253 vraddhn.s32 d12, q0, q4
254 vraddhn.s32 d13, q0, q5
263 vraddhn.s32 d12, q0, q4
264 vraddhn.s32 d13, q0, q5
273 vraddhn.s32 d12, q0, q4
274 vraddhn.s32 d13, q0, q5
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | neont2-add-encoding.s.cs | 63 0xc0,0xff,0xa2,0x04 = vraddhn.i16 d16, q8, q9
64 0xd0,0xff,0xa2,0x04 = vraddhn.i32 d16, q8, q9
65 0xe0,0xff,0xa2,0x04 = vraddhn.i64 d16, q8, q9
|
| D | neon-add-encoding.s.cs | 103 0xa2,0x04,0xc0,0xf3 = vraddhn.i16 d16, q8, q9
104 0xa2,0x04,0xd0,0xf3 = vraddhn.i32 d16, q8, q9
105 0xa2,0x04,0xe0,0xf3 = vraddhn.i64 d16, q8, q9
|
| /external/arm-neon-tests/ |
| D | ref_vraddhn.c | 26 #define INSN_NAME vraddhn
|
| D | Makefile.gcc | 56 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
|
| D | Makefile | 50 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
|
| /external/llvm-project/llvm/test/tools/llvm-mca/ARM/ |
| D | cortex-a57-neon-instructions.s | 118 vraddhn.i16 d16, q8, q9
119 vraddhn.i32 d16, q8, q9
120 vraddhn.i64 d16, q8, q9
1234 # CHECK-NEXT: 1 3 0.50 vraddhn.i16 d16, q8, q9
1235 # CHECK-NEXT: 1 3 0.50 vraddhn.i32 d16, q8, q9
1236 # CHECK-NEXT: 1 3 0.50 vraddhn.i64 d16, q8, q9
2357 # CHECK-NEXT: - - - - - - 0.50 0.50 vraddhn.i16 d16, q8, q9
2358 # CHECK-NEXT: - - - - - - 0.50 0.50 vraddhn.i32 d16, q8, q9
2359 # CHECK-NEXT: - - - - - - 0.50 0.50 vraddhn.i64 d16, q8, q9
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 242 # CHECK: vraddhn.i16 d16, q8, q9
244 # CHECK: vraddhn.i32 d16, q8, q9
246 # CHECK: vraddhn.i64 d16, q8, q9
|
| D | neon.txt | 245 # CHECK: vraddhn.i16 d16, q8, q9
247 # CHECK: vraddhn.i32 d16, q8, q9
249 # CHECK: vraddhn.i64 d16, q8, q9
|
| /external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 242 # CHECK: vraddhn.i16 d16, q8, q9
244 # CHECK: vraddhn.i32 d16, q8, q9
246 # CHECK: vraddhn.i64 d16, q8, q9
|
| D | neon.txt | 245 # CHECK: vraddhn.i16 d16, q8, q9
247 # CHECK: vraddhn.i32 d16, q8, q9
249 # CHECK: vraddhn.i64 d16, q8, q9
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 429 def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>;
515 def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">;
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 136 def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>;
315 def VRADDHN : IInst<"vraddhn", "<QQ", "silUsUiUl">;
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5481 void vraddhn(
5483 void vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vraddhn() function
5484 vraddhn(al, dt, rd, rn, rm); in vraddhn()
|
| D | disasm-aarch32.h | 2290 void vraddhn(
|
| D | disasm-aarch32.cc | 6044 void Disassembler::vraddhn( in vraddhn() function in vixl::aarch32::Disassembler
28763 vraddhn(CurrentCond(), in DecodeT32()
42920 vraddhn(al, in DecodeA32()
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 3943 { /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64 $vd, $vn, $vm */
3946 { /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32 $vd, $vn, $vm */
3949 { /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16 $vd, $vn, $vm */
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 3943 { /* ARM_VRADDHNv2i32, ARM_INS_VRADDHN: vraddhn${p}.i64 $vd, $vn, $vm */
3946 { /* ARM_VRADDHNv4i16, ARM_INS_VRADDHN: vraddhn${p}.i32 $vd, $vn, $vm */
3949 { /* ARM_VRADDHNv8i8, ARM_INS_VRADDHN: vraddhn${p}.i16 $vd, $vn, $vm */
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9946 "shrunb\010vqshrunt\005vqsub\007vraddhn\006vrecpe\006vrecps\006vrev16\006"
14126 …{ 3354 /* vraddhn */, ARM::VRADDHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNEO…
14127 …{ 3354 /* vraddhn */, ARM::VRADDHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNE…
14128 …{ 3354 /* vraddhn */, ARM::VRADDHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, AMFBS_HasNE…
|