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/external/llvm-project/llvm/test/MC/ARM/
Dneont2-shift-encoding.s93 @ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0x40,0xef,0xa1,0x05]
94 vrshl.s8 d16, d17, d16
95 @ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0x50,0xef,0xa1,0x05]
96 vrshl.s16 d16, d17, d16
97 @ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0x60,0xef,0xa1,0x05]
98 vrshl.s32 d16, d17, d16
99 @ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0x70,0xef,0xa1,0x05]
100 vrshl.s64 d16, d17, d16
101 @ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0x40,0xff,0xa1,0x05]
102 vrshl.u8 d16, d17, d16
[all …]
Dneon-shift-encoding.s281 vrshl.s8 d16, d17, d16
282 vrshl.s16 d16, d17, d16
283 vrshl.s32 d16, d17, d16
284 vrshl.s64 d16, d17, d16
285 vrshl.u8 d16, d17, d16
286 vrshl.u16 d16, d17, d16
287 vrshl.u32 d16, d17, d16
288 vrshl.u64 d16, d17, d16
289 vrshl.s8 q8, q9, q8
290 vrshl.s16 q8, q9, q8
[all …]
Dmve-shifts.s321 # CHECK: vrshl.s8 q0, q6, q4 @ encoding: [0x08,0xef,0x4c,0x05]
322 # CHECK-NOFP: vrshl.s8 q0, q6, q4 @ encoding: [0x08,0xef,0x4c,0x05]
323 vrshl.s8 q0, q6, q4
325 # CHECK: vrshl.s16 q1, q4, q7 @ encoding: [0x1e,0xef,0x48,0x25]
326 # CHECK-NOFP: vrshl.s16 q1, q4, q7 @ encoding: [0x1e,0xef,0x48,0x25]
327 vrshl.s16 q1, q4, q7
329 # CHECK: vrshl.s32 q1, q4, q4 @ encoding: [0x28,0xef,0x48,0x25]
330 # CHECK-NOFP: vrshl.s32 q1, q4, q4 @ encoding: [0x28,0xef,0x48,0x25]
331 vrshl.s32 q1, q4, q4
333 # CHECK: vrshl.u8 q0, q3, q5 @ encoding: [0x0a,0xff,0x46,0x05]
[all …]
Dmve-qdest-rsrc.s207 # CHECK: vrshl.s8 q0, r6 @ encoding: [0x33,0xee,0x66,0x1e]
208 # CHECK-NOFP: vrshl.s8 q0, r6 @ encoding: [0x33,0xee,0x66,0x1e]
209 vrshl.s8 q0, r6
211 # CHECK: vrshl.s16 q0, lr @ encoding: [0x37,0xee,0x6e,0x1e]
212 # CHECK-NOFP: vrshl.s16 q0, lr @ encoding: [0x37,0xee,0x6e,0x1e]
213 vrshl.s16 q0, lr
215 # CHECK: vrshl.s32 q0, r4 @ encoding: [0x3b,0xee,0x64,0x1e]
216 # CHECK-NOFP: vrshl.s32 q0, r4 @ encoding: [0x3b,0xee,0x64,0x1e]
217 vrshl.s32 q0, r4
219 # CHECK: vrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0x60,0x1e]
[all …]
/external/llvm/test/MC/ARM/
Dneont2-shift-encoding.s93 @ CHECK: vrshl.s8 d16, d17, d16 @ encoding: [0x40,0xef,0xa1,0x05]
94 vrshl.s8 d16, d17, d16
95 @ CHECK: vrshl.s16 d16, d17, d16 @ encoding: [0x50,0xef,0xa1,0x05]
96 vrshl.s16 d16, d17, d16
97 @ CHECK: vrshl.s32 d16, d17, d16 @ encoding: [0x60,0xef,0xa1,0x05]
98 vrshl.s32 d16, d17, d16
99 @ CHECK: vrshl.s64 d16, d17, d16 @ encoding: [0x70,0xef,0xa1,0x05]
100 vrshl.s64 d16, d17, d16
101 @ CHECK: vrshl.u8 d16, d17, d16 @ encoding: [0x40,0xff,0xa1,0x05]
102 vrshl.u8 d16, d17, d16
[all …]
Dneon-shift-encoding.s281 vrshl.s8 d16, d17, d16
282 vrshl.s16 d16, d17, d16
283 vrshl.s32 d16, d17, d16
284 vrshl.s64 d16, d17, d16
285 vrshl.u8 d16, d17, d16
286 vrshl.u16 d16, d17, d16
287 vrshl.u32 d16, d17, d16
288 vrshl.u64 d16, d17, d16
289 vrshl.s8 q8, q9, q8
290 vrshl.s16 q8, q9, q8
[all …]
/external/capstone/suite/MC/ARM/
Dneont2-shift-encoding.s.cs46 0x40,0xef,0xa1,0x05 = vrshl.s8 d16, d17, d16
47 0x50,0xef,0xa1,0x05 = vrshl.s16 d16, d17, d16
48 0x60,0xef,0xa1,0x05 = vrshl.s32 d16, d17, d16
49 0x70,0xef,0xa1,0x05 = vrshl.s64 d16, d17, d16
50 0x40,0xff,0xa1,0x05 = vrshl.u8 d16, d17, d16
51 0x50,0xff,0xa1,0x05 = vrshl.u16 d16, d17, d16
52 0x60,0xff,0xa1,0x05 = vrshl.u32 d16, d17, d16
53 0x70,0xff,0xa1,0x05 = vrshl.u64 d16, d17, d16
54 0x40,0xef,0xe2,0x05 = vrshl.s8 q8, q9, q8
55 0x50,0xef,0xe2,0x05 = vrshl.s16 q8, q9, q8
[all …]
Dneon-shift-encoding.s.cs126 0xa1,0x05,0x40,0xf2 = vrshl.s8 d16, d17, d16
127 0xa1,0x05,0x50,0xf2 = vrshl.s16 d16, d17, d16
128 0xa1,0x05,0x60,0xf2 = vrshl.s32 d16, d17, d16
129 0xa1,0x05,0x70,0xf2 = vrshl.s64 d16, d17, d16
130 0xa1,0x05,0x40,0xf3 = vrshl.u8 d16, d17, d16
131 0xa1,0x05,0x50,0xf3 = vrshl.u16 d16, d17, d16
132 0xa1,0x05,0x60,0xf3 = vrshl.u32 d16, d17, d16
133 0xa1,0x05,0x70,0xf3 = vrshl.u64 d16, d17, d16
134 0xe2,0x05,0x40,0xf2 = vrshl.s8 q8, q9, q8
135 0xe2,0x05,0x50,0xf2 = vrshl.s16 q8, q9, q8
[all …]
/external/libavc/common/arm/
Dih264_weighted_pred_a9q.s148 vrshl.s16 q2, q2, q0 @rounds off the weighted samples from rows 1,2
149 vrshl.s16 q3, q3, q0 @rounds off the weighted samples from rows 3,4
182 vrshl.s16 q2, q2, q0 @rounds off the weighted samples from row 1
183 vrshl.s16 q3, q3, q0 @rounds off the weighted samples from row 2
184 vrshl.s16 q4, q4, q0 @rounds off the weighted samples from row 3
186 vrshl.s16 q5, q5, q0 @rounds off the weighted samples from row 4
229 vrshl.s16 q6, q6, q0 @rounds off the weighted samples from row 1L
232 vrshl.s16 q7, q7, q0 @rounds off the weighted samples from row 1H
233 vrshl.s16 q8, q8, q0 @rounds off the weighted samples from row 2L
235 vrshl.s16 q9, q9, q0 @rounds off the weighted samples from row 2H
[all …]
Dih264_weighted_bi_pred_a9q.s190 vrshl.s16 q2, q2, q0 @rounds off the weighted samples from rows 1,2
191 vrshl.s16 q4, q4, q0 @rounds off the weighted samples from rows 3,4
238 vrshl.s16 q2, q2, q0 @rounds off the weighted samples from row 1
239 vrshl.s16 q4, q4, q0 @rounds off the weighted samples from row 2
240 vrshl.s16 q6, q6, q0 @rounds off the weighted samples from row 3
242 vrshl.s16 q8, q8, q0 @rounds off the weighted samples from row 4
311 vrshl.s16 q10, q10, q0 @rounds off the weighted samples from row 1L
315 vrshl.s16 q2, q2, q0 @rounds off the weighted samples from row 1H
317 vrshl.s16 q12, q12, q0 @rounds off the weighted samples from row 2L
319 vrshl.s16 q4, q4, q0 @rounds off the weighted samples from row 2H
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvshl.ll366 ;CHECK: vrshl.s8
375 ;CHECK: vrshl.s16
384 ;CHECK: vrshl.s32
393 ;CHECK: vrshl.s64
402 ;CHECK: vrshl.u8
411 ;CHECK: vrshl.u16
420 ;CHECK: vrshl.u32
429 ;CHECK: vrshl.u64
438 ;CHECK: vrshl.s8
447 ;CHECK: vrshl.s16
[all …]
/external/llvm/test/CodeGen/ARM/
Dvshl.ll366 ;CHECK: vrshl.s8
375 ;CHECK: vrshl.s16
384 ;CHECK: vrshl.s32
393 ;CHECK: vrshl.s64
402 ;CHECK: vrshl.u8
411 ;CHECK: vrshl.u16
420 ;CHECK: vrshl.u32
429 ;CHECK: vrshl.u64
438 ;CHECK: vrshl.s8
447 ;CHECK: vrshl.s16
[all …]
/external/llvm-project/llvm/test/tools/llvm-mca/ARM/
Dcortex-a57-neon-instructions.s613 vrshl.s8 d16, d17, d16
614 vrshl.s16 d16, d17, d16
615 vrshl.s32 d16, d17, d16
616 vrshl.s64 d16, d17, d16
617 vrshl.u8 d16, d17, d16
618 vrshl.u16 d16, d17, d16
619 vrshl.u32 d16, d17, d16
620 vrshl.u64 d16, d17, d16
621 vrshl.s8 q8, q9, q8
622 vrshl.s16 q8, q9, q8
[all …]
/external/arm-neon-tests/
DMakefile.gcc50 vmlsl_lane vmovl vmovn vmull vmull_lane vrev vrshl vshl_n \
DMakefile44 vmlsl_lane vmovl vmovn vmull vmull_lane vrev vrshl vshl_n \
Dref_vrshl.c40 vrshl##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \ in exec_vrshl()
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dmve-qdest-rsrc.txt206 # CHECK: vrshl.s8 q0, r6 @ encoding: [0x33,0xee,0x66,0x1e]
210 # CHECK: vrshl.s16 q0, lr @ encoding: [0x37,0xee,0x6e,0x1e]
214 # CHECK: vrshl.s32 q0, r4 @ encoding: [0x3b,0xee,0x64,0x1e]
218 # CHECK: vrshl.u8 q0, r0 @ encoding: [0x33,0xfe,0x60,0x1e]
222 # CHECK: vrshl.u16 q0, r10 @ encoding: [0x37,0xfe,0x6a,0x1e]
226 # CHECK: vrshl.u32 q0, r1 @ encoding: [0x3b,0xfe,0x61,0x1e]
Dmve-shifts.txt257 # CHECK: vrshl.s8 q0, q6, q4 @ encoding: [0x08,0xef,0x4c,0x05]
261 # CHECK: vrshl.s16 q1, q4, q7 @ encoding: [0x1e,0xef,0x48,0x25]
265 # CHECK: vrshl.s32 q1, q4, q4 @ encoding: [0x28,0xef,0x48,0x25]
269 # CHECK: vrshl.u8 q0, q3, q5 @ encoding: [0x0a,0xff,0x46,0x05]
273 # CHECK: vrshl.u16 q5, q6, q5 @ encoding: [0x1a,0xff,0x4c,0xa5]
277 # CHECK: vrshl.u32 q1, q7, q3 @ encoding: [0x26,0xff,0x4e,0x25]
Dneont2.txt1118 # CHECK: vrshl.s8 d16, d17, d16
1120 # CHECK: vrshl.s16 d16, d17, d16
1122 # CHECK: vrshl.s32 d16, d17, d16
1124 # CHECK: vrshl.s64 d16, d17, d16
1126 # CHECK: vrshl.u8 d16, d17, d16
1128 # CHECK: vrshl.u16 d16, d17, d16
1130 # CHECK: vrshl.u32 d16, d17, d16
1132 # CHECK: vrshl.u64 d16, d17, d16
1134 # CHECK: vrshl.s8 q8, q9, q8
1136 # CHECK: vrshl.s16 q8, q9, q8
[all …]
Dneon.txt1294 # CHECK: vrshl.s8 d16, d17, d16
1296 # CHECK: vrshl.s16 d16, d17, d16
1298 # CHECK: vrshl.s32 d16, d17, d16
1300 # CHECK: vrshl.s64 d16, d17, d16
1302 # CHECK: vrshl.u8 d16, d17, d16
1304 # CHECK: vrshl.u16 d16, d17, d16
1306 # CHECK: vrshl.u32 d16, d17, d16
1308 # CHECK: vrshl.u64 d16, d17, d16
1310 # CHECK: vrshl.s8 q8, q9, q8
1312 # CHECK: vrshl.s16 q8, q9, q8
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt1108 # CHECK: vrshl.s8 d16, d17, d16
1110 # CHECK: vrshl.s16 d16, d17, d16
1112 # CHECK: vrshl.s32 d16, d17, d16
1114 # CHECK: vrshl.s64 d16, d17, d16
1116 # CHECK: vrshl.u8 d16, d17, d16
1118 # CHECK: vrshl.u16 d16, d17, d16
1120 # CHECK: vrshl.u32 d16, d17, d16
1122 # CHECK: vrshl.u64 d16, d17, d16
1124 # CHECK: vrshl.s8 q8, q9, q8
1126 # CHECK: vrshl.s16 q8, q9, q8
[all …]
Dneon.txt1285 # CHECK: vrshl.s8 d16, d17, d16
1287 # CHECK: vrshl.s16 d16, d17, d16
1289 # CHECK: vrshl.s32 d16, d17, d16
1291 # CHECK: vrshl.s64 d16, d17, d16
1293 # CHECK: vrshl.u8 d16, d17, d16
1295 # CHECK: vrshl.u16 d16, d17, d16
1297 # CHECK: vrshl.u32 d16, d17, d16
1299 # CHECK: vrshl.u64 d16, d17, d16
1301 # CHECK: vrshl.s8 q8, q9, q8
1303 # CHECK: vrshl.s16 q8, q9, q8
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvector-shift-var.ll247 ; CHECK-NEXT: vrshl.s8 q0, q0, q1
257 ; CHECK-NEXT: vrshl.s16 q0, q0, q1
267 ; CHECK-NEXT: vrshl.s32 q0, q0, q1
277 ; CHECK-NEXT: vrshl.u8 q0, q0, q1
287 ; CHECK-NEXT: vrshl.u16 q0, q0, q1
297 ; CHECK-NEXT: vrshl.u32 q0, q0, q1
307 ; CHECK-NEXT: vrshl.s8 q0, r0
317 ; CHECK-NEXT: vrshl.s16 q0, r0
327 ; CHECK-NEXT: vrshl.s32 q0, r0
337 ; CHECK-NEXT: vrshl.u8 q0, r0
[all …]
/external/capstone/arch/AArch64/
DARMMappingInsnOp.inc4120 { /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */
4123 { /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */
4126 { /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */
4129 { /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */
4132 { /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */
4135 { /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */
4138 { /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */
4141 { /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */
4144 { /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */
4147 { /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */
[all …]
/external/capstone/arch/ARM/
DARMMappingInsnOp.inc4120 { /* ARM_VRSHLsv16i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */
4123 { /* ARM_VRSHLsv1i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */
4126 { /* ARM_VRSHLsv2i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */
4129 { /* ARM_VRSHLsv2i64, ARM_INS_VRSHL: vrshl${p}.s64 $vd, $vm, $vn */
4132 { /* ARM_VRSHLsv4i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */
4135 { /* ARM_VRSHLsv4i32, ARM_INS_VRSHL: vrshl${p}.s32 $vd, $vm, $vn */
4138 { /* ARM_VRSHLsv8i16, ARM_INS_VRSHL: vrshl${p}.s16 $vd, $vm, $vn */
4141 { /* ARM_VRSHLsv8i8, ARM_INS_VRSHL: vrshl${p}.s8 $vd, $vm, $vn */
4144 { /* ARM_VRSHLuv16i8, ARM_INS_VRSHL: vrshl${p}.u8 $vd, $vm, $vn */
4147 { /* ARM_VRSHLuv1i64, ARM_INS_VRSHL: vrshl${p}.u64 $vd, $vm, $vn */
[all …]

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