/external/llvm-project/llvm/test/MC/Disassembler/ARM/ |
D | mve-load-store.txt | 1085 # CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f] 1089 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f] 1093 # CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f] 1097 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f] 1101 # CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f] 1221 # CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f] 1225 # CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff] 1229 # CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff] 1233 # CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff] 1237 # CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff] [all …]
|
/external/swiftshader/third_party/subzero/src/ |
D | IceAssemblerARM32.h | 597 void vstrd(const Operand *OpDd, const Operand *OpAddress, 600 void vstrd(const Operand *OpDd, const Operand *OpAddress, in vstrd() function 603 vstrd(OpDd, OpAddress, Cond, TInfo); in vstrd()
|
D | IceInstARM32.cpp | 2790 Asm->vstrd(Src0, Src1, getPredicate(), Func->getTarget()); in emitIAS()
|
D | IceAssemblerARM32.cpp | 3685 void AssemblerARM32::vstrd(const Operand *OpDd, const Operand *OpAddress, in vstrd() function in Ice::ARM32::AssemblerARM32
|
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
D | scatter-gather.ll | 1245 ; CHECK-NEXT: vstrd.64 q1, [q0, #408] 1257 ; CHECK-NEXT: vstrd.64 q1, [q0, #-472] 1306 ; CHECK-NEXT: vstrd.64 q0, [q1, #208]! 1322 ; CHECK-NEXT: vstrd.64 q0, [q1, #-168]! 1365 ; CHECK-NEXT: vstrd.64 q1, [r0, q0] 1377 ; CHECK-NEXT: vstrd.64 q1, [r0, q0] 1415 ; CHECK-NEXT: vstrd.64 q1, [r0, q0, uxtw #3] 1425 ; CHECK-NEXT: vstrd.64 q1, [r0, q0, uxtw #3]
|
/external/swiftshader/third_party/subzero/src/DartARM32/ |
D | assembler_arm.h | 645 void vstrd(DRegister dd, Address ad, Condition cond = AL);
|
D | assembler_arm.cc | 763 void Assembler::vstrd(DRegister dd, Address ad, Condition cond) { in vstrd() function in dart::Assembler 2808 vstrd(reg, Address(base, offset), cond); in StoreDToOffset()
|
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 1733 Mnemonic = "vstrd.64"; // "vstrd.f64" 1738 Mnemonic = "vstrd.64"; // "vstrd.s64" 1743 Mnemonic = "vstrd.64"; // "vstrd.u64" 9956 "r\005vstrb\005vstrd\005vstrh\005vstrw\004vsub\006vsubhn\005vsubl\005vsu" 14948 …{ 3851 /* vstrd */, ARM::MVE_VSTRD64_qi, Convert__Reg1_2__MemRegQS3Offset2_3__VPTPredN2_0, AMFBS_H… 14949 …{ 3851 /* vstrd */, ARM::MVE_VSTRD64_rq_u, Convert__Reg1_2__MemRegRQS0Offset2_3__VPTPredN2_0, AMFB… 14950 …{ 3851 /* vstrd */, ARM::MVE_VSTRD64_rq, Convert__Reg1_2__MemRegRQS3Offset2_3__VPTPredN2_0, AMFBS_… 14951 …{ 3851 /* vstrd */, ARM::MVE_VSTRD64_qi_pre, Convert__imm_95_0__Reg1_2__MemRegQS3Offset2_3__VPTPre…
|