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Searched refs:vswp (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-vswp.s3 vswp d1, d2 define
4 vswp q1, q2 label
6 @ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
7 @ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
/external/llvm-project/llvm/test/MC/ARM/
Dneon-vswp.s3 vswp d1, d2 define
4 vswp q1, q2 label
6 @ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
7 @ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
/external/capstone/suite/MC/ARM/
Dneon-vswp.s.cs2 0x02,0x10,0xb2,0xf3 = vswp d1, d2
3 0x44,0x20,0xb2,0xf3 = vswp q1, q2
/external/libavc/common/arm/
Dih264_iquant_itrans_recon_a9.s179 vswp d6, d7 @Reverse positions of x2 and x3 define
186 vswp d12, d13
204 vswp d16, d17 @Reverse positions of x2 and x3
209 vswp d22, d23
353 vswp d6, d7 @Reverse positions of x2 and x3 define
361 vswp d12, d13
379 vswp d16, d17 @Reverse positions of x2 and x3
385 vswp d22, d23
601 vswp d1, d8 @ Q0/Q1 = Row order x0/x1 define
602 vswp d3, d10 @ Q2/Q3 = Row order x2/x3 define
[all …]
Dih264_ihadamard_scaling_a9.s126 vswp d5, d8 @Q2 = x4, Q4 = x6 define
127 vswp d7, d10 @Q3 = x5, Q5 = x7 define
Dih264_resi_trans_quant_a9.s500 vswp d15, d18
501 vswp d17, d20
/external/libxaac/decoder/armv7/
Dixheaacd_esbr_fwd_modulation.s46 vswp d4, d7 define
47 vswp d5, d6 define
/external/libhevc/common/arm/
Dihevc_itrans_recon_8x8.s534 vswp d3,d6 define
537 vswp d5,d8 define
768 vswp d3,d6 define
771 vswp d5,d8 define
858 vswp d11,d14
859 vswp d13,d16
Dihevc_itrans_recon_16x16.s1071 vswp d5,d18 define
1072 vswp d23,d14
1073 vswp d13,d20
1074 vswp d31,d8
Dihevc_itrans_recon_32x32.s2758 vswp d13,d16
2759 vswp d21,d24
2760 vswp d15,d18
2761 vswp d23,d26
2823 vswp d13,d16
2824 vswp d21,d24
2825 vswp d15,d18
2826 vswp d23,d26
/external/libmpeg2/common/arm/
Dimpeg2_idct.s802 vswp d3, d6 define
805 vswp d5, d8 define
1040 vswp d3, d6 define
1043 vswp d5, d8 define
1130 vswp d11, d14
1131 vswp d13, d16
/external/libvpx/libvpx/vpx_dsp/arm/
Didct4x4_add_neon.asm103 vswp d18, d19
Dloopfilter_16_neon.asm219 vswp d23, d25
/external/libvpx/config/arm-neon/vpx_dsp/arm/
Didct4x4_add_neon.asm.S110 vswp d18, d19
Dloopfilter_16_neon.asm.S231 vswp d23, d25
/external/vixl/src/aarch32/
Dassembler-aarch32.h6067 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
6068 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6069 void vswp(DRegister rd, DRegister rm) { in vswp() function
6070 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
6072 void vswp(Condition cond, DRegister rd, DRegister rm) { in vswp() function
6073 vswp(cond, kDataTypeValueNone, rd, rm); in vswp()
6076 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
6077 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6078 void vswp(QRegister rd, QRegister rm) { in vswp() function
6079 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
[all …]
Ddisasm-aarch32.h2591 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
2593 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
/external/boringssl/src/crypto/poly1305/
Dpoly1305_arm_asm.S683 # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top
684 # asm 2: vswp <d23=d2,<d01=d23
685 vswp d2,d23 define
/external/rust/crates/ring/crypto/poly1305/
Dpoly1305_arm_asm.S685 # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top
686 # asm 2: vswp <d23=d2,<d01=d23
687 vswp d2,d23 define
/external/rust/crates/quiche/deps/boringssl/src/crypto/poly1305/
Dpoly1305_arm_asm.S683 # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top
684 # asm 2: vswp <d23=d2,<d01=d23
685 vswp d2,d23 define
/external/libavc/encoder/arm/
Dime_distortion_metrics_a9q.s1045 vswp d10, d11 @I rearrange so that the q4 and q5 add properly
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc1190 Mnemonic = "vswp";
9957 "bw\004vswp\004vtbl\004vtbx\004vtrn\004vtst\005vudot\004vuzp\004vzip\003"
15030 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_Has…
15031 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, AMFBS_Has…
15032 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15033 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15034 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15035 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15036 …{ 3893 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
15037 …{ 3893 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, AMFBS_Has…
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td5675 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5679 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
8105 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8107 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8169 def : NEONMnemonicAlias<"vswpq", "vswp">;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td6121 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6125 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
8841 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8843 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8905 def : NEONMnemonicAlias<"vswpq", "vswp">;
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td6119 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6123 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
8960 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8962 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
9024 def : NEONMnemonicAlias<"vswpq", "vswp">;

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