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Searched refs:vuzp (Results 1 – 25 of 58) sorted by relevance

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/external/llvm-project/llvm/test/MC/ARM/
Dneont2-shuffle-encoding.s29 @ CHECK: vuzp.8 d17, d16 @ encoding: [0xf2,0xff,0x20,0x11]
30 vuzp.8 d17, d16
31 @ CHECK: vuzp.16 d17, d16 @ encoding: [0xf6,0xff,0x20,0x11]
32 vuzp.16 d17, d16
33 @ CHECK: vuzp.8 q9, q8 @ encoding: [0xf2,0xff,0x60,0x21]
34 vuzp.8 q9, q8
35 @ CHECK: vuzp.16 q9, q8 @ encoding: [0xf6,0xff,0x60,0x21]
36 vuzp.16 q9, q8
37 @ CHECK: vuzp.32 q9, q8 @ encoding: [0xfa,0xff,0x60,0x21]
38 vuzp.32 q9, q8
Dneont2-sub-encoding.s27 @ CHECK: vuzp.8 d17, d16 @ encoding: [0xf2,0xff,0x20,0x11]
28 vuzp.8 d17, d16
29 @ CHECK: vuzp.16 d17, d16 @ encoding: [0xf6,0xff,0x20,0x11]
30 vuzp.16 d17, d16
31 @ CHECK: vuzp.8 q9, q8 @ encoding: [0xf2,0xff,0x60,0x21]
32 vuzp.8 q9, q8
33 @ CHECK: vuzp.16 q9, q8 @ encoding: [0xf6,0xff,0x60,0x21]
34 vuzp.16 q9, q8
35 @ CHECK: vuzp.32 q9, q8 @ encoding: [0xfa,0xff,0x60,0x21]
36 vuzp.32 q9, q8
Dneon-shuffle-encoding.s52 vuzp.8 d17, d16
53 vuzp.16 d17, d16
54 vuzp.8 q9, q8
55 vuzp.16 q9, q8
56 vuzp.32 q9, q8
63 vuzp.32 d2, d3
65 @ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3]
66 @ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3]
67 @ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3]
68 @ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3]
[all …]
/external/llvm/test/MC/ARM/
Dneont2-shuffle-encoding.s29 @ CHECK: vuzp.8 d17, d16 @ encoding: [0xf2,0xff,0x20,0x11]
30 vuzp.8 d17, d16
31 @ CHECK: vuzp.16 d17, d16 @ encoding: [0xf6,0xff,0x20,0x11]
32 vuzp.16 d17, d16
33 @ CHECK: vuzp.8 q9, q8 @ encoding: [0xf2,0xff,0x60,0x21]
34 vuzp.8 q9, q8
35 @ CHECK: vuzp.16 q9, q8 @ encoding: [0xf6,0xff,0x60,0x21]
36 vuzp.16 q9, q8
37 @ CHECK: vuzp.32 q9, q8 @ encoding: [0xfa,0xff,0x60,0x21]
38 vuzp.32 q9, q8
Dneont2-sub-encoding.s27 @ CHECK: vuzp.8 d17, d16 @ encoding: [0xf2,0xff,0x20,0x11]
28 vuzp.8 d17, d16
29 @ CHECK: vuzp.16 d17, d16 @ encoding: [0xf6,0xff,0x20,0x11]
30 vuzp.16 d17, d16
31 @ CHECK: vuzp.8 q9, q8 @ encoding: [0xf2,0xff,0x60,0x21]
32 vuzp.8 q9, q8
33 @ CHECK: vuzp.16 q9, q8 @ encoding: [0xf6,0xff,0x60,0x21]
34 vuzp.16 q9, q8
35 @ CHECK: vuzp.32 q9, q8 @ encoding: [0xfa,0xff,0x60,0x21]
36 vuzp.32 q9, q8
Dneon-shuffle-encoding.s52 vuzp.8 d17, d16
53 vuzp.16 d17, d16
54 vuzp.8 q9, q8
55 vuzp.16 q9, q8
56 vuzp.32 q9, q8
63 vuzp.32 d2, d3
65 @ CHECK: vuzp.8 d17, d16 @ encoding: [0x20,0x11,0xf2,0xf3]
66 @ CHECK: vuzp.16 d17, d16 @ encoding: [0x20,0x11,0xf6,0xf3]
67 @ CHECK: vuzp.8 q9, q8 @ encoding: [0x60,0x21,0xf2,0xf3]
68 @ CHECK: vuzp.16 q9, q8 @ encoding: [0x60,0x21,0xf6,0xf3]
[all …]
/external/capstone/suite/MC/ARM/
Dneont2-sub-encoding.s.cs14 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16
15 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16
16 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8
17 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8
18 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8
Dneont2-shuffle-encoding.s.cs14 0xf2,0xff,0x20,0x11 = vuzp.8 d17, d16
15 0xf6,0xff,0x20,0x11 = vuzp.16 d17, d16
16 0xf2,0xff,0x60,0x21 = vuzp.8 q9, q8
17 0xf6,0xff,0x60,0x21 = vuzp.16 q9, q8
18 0xfa,0xff,0x60,0x21 = vuzp.32 q9, q8
Dneon-shuffle-encoding.s.cs22 0x20,0x11,0xf2,0xf3 = vuzp.8 d17, d16
23 0x20,0x11,0xf6,0xf3 = vuzp.16 d17, d16
24 0x60,0x21,0xf2,0xf3 = vuzp.8 q9, q8
25 0x60,0x21,0xf6,0xf3 = vuzp.16 q9, q8
26 0x60,0x21,0xfa,0xf3 = vuzp.32 q9, q8
/external/llvm-project/llvm/test/CodeGen/AArch64/
Daarch64-vuzp.ll10 …%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4…
12 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
21 …%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5…
23 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
32 …%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4…
34 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
43 …%vuzp.i212.1 = shufflevector <16 x i8> %vtbl1.i.1, <16 x i8> undef, <8 x i32> <i32 3, i32 3, i32 5…
45 store <8 x i8> %vuzp.i212.1, <8 x i8>* %scevgep, align 1
Dneon-perm.ll2483 …%vuzp.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i3…
2485 %.fca.0.0.insert = insertvalue %struct.int8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0
2495 %vuzp.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
2497 %.fca.0.0.insert = insertvalue %struct.int16x4x2_t undef, <4 x i16> %vuzp.i, 0, 0
2507 %vuzp.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2>
2509 %.fca.0.0.insert = insertvalue %struct.int32x2x2_t undef, <2 x i32> %vuzp.i, 0, 0
2519 …%vuzp.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i3…
2521 %.fca.0.0.insert = insertvalue %struct.uint8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0
2531 %vuzp.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
2533 %.fca.0.0.insert = insertvalue %struct.uint16x4x2_t undef, <4 x i16> %vuzp.i, 0, 0
[all …]
/external/llvm/test/CodeGen/ARM/
Dvuzp.ll8 ; CHECK-NEXT: vuzp.8 d17, d16
25 ; CHECK-NEXT: vuzp.8 [[LDR0]], [[LDR1]]
40 ; CHECK-NEXT: vuzp.16 d17, d16
57 ; CHECK-NEXT: vuzp.16 [[LDR0]], [[LDR1]]
74 ; CHECK-NEXT: vuzp.8 q9, q8
92 ; CHECK-NEXT: vuzp.8 q9, q8
107 ; CHECK-NEXT: vuzp.16 q9, q8
125 ; CHECK-NEXT: vuzp.16 q9, q8
140 ; CHECK-NEXT: vuzp.32 q9, q8
158 ; CHECK-NEXT: vuzp.32 q9, q8
[all …]
Dbig-endian-neon-trunc-store.ll7 ; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
19 ; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
Dpopcnt.ll25 ; CHECK: vuzp.8 {{d[0-9]+}}, {{d[0-9]+}}
37 ; CHECK: vuzp.8 {{q[0-9]+}}, {{q[0-9]+}}
49 ; CHECK: vuzp.8 {{d[0-9]+}}, {{d[0-9]+}}
52 ; CHECK: vuzp.16 {{d[0-9]+}}, {{d[0-9]+}}
64 ; CHECK: vuzp.8 {{q[0-9]+}}, {{q[0-9]+}}
67 ; CHECK: vuzp.16 {{q[0-9]+}}, {{q[0-9]+}}
Dbig-endian-neon-extend.ll69 ; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvuzp.ll9 ; CHECK-NEXT: vuzp.8 d17, d16
26 ; CHECK-NEXT: vuzp.8 d16, d17
41 ; CHECK-NEXT: vuzp.16 d17, d16
58 ; CHECK-NEXT: vuzp.16 d16, d17
75 ; CHECK-NEXT: vuzp.8 q9, q8
93 ; CHECK-NEXT: vuzp.8 q9, q8
108 ; CHECK-NEXT: vuzp.16 q9, q8
126 ; CHECK-NEXT: vuzp.16 q9, q8
141 ; CHECK-NEXT: vuzp.32 q9, q8
159 ; CHECK-NEXT: vuzp.32 q9, q8
[all …]
Dbig-endian-neon-trunc-store.ll7 ; CHECK: vuzp.16 [[REG]], [[REG2:d[0-9]+]]
19 ; CHECK: vuzp.8 [[REG]], [[REG2:d[0-9]+]]
Da15-partial-update.ll37 ; CHECK-NEXT: vuzp.8 d16, d18
73 ; CHECK-NEXT: vuzp.8 d16, d18
Dvpadd.ll216 ; Combine vuzp+vadd->vpadd.
233 ; Combine vuzp+vadd->vpadd.
265 ; Combine vuzp+vaddl->vpaddl
283 ; Combine vuzp+vaddl->vpaddl
306 ; Combine vuzp+vaddl->vpaddl
332 ; CHECK-NEXT: vuzp.16 q8, q9
345 ; Combine vuzp+vaddl->vpaddl
385 ; Combine vuzp+vaddl->vpaddl
403 ; Combine vuzp+vaddl->vpaddl
Dvext.ll188 ; CHECK-NEXT: vuzp.16 d16, d18
244 ; CHECK-NEXT: vuzp.16 d18, d17
268 ; CHECK-NEXT: vuzp.16 d22, d23
269 ; CHECK-NEXT: vuzp.16 d22, d18
Dbig-endian-neon-extend.ll69 ; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
/external/llvm/test/CodeGen/AArch64/
Dneon-perm.ll2483 …%vuzp.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i3…
2485 %.fca.0.0.insert = insertvalue %struct.int8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0
2495 %vuzp.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
2497 %.fca.0.0.insert = insertvalue %struct.int16x4x2_t undef, <4 x i16> %vuzp.i, 0, 0
2507 %vuzp.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2>
2509 %.fca.0.0.insert = insertvalue %struct.int32x2x2_t undef, <2 x i32> %vuzp.i, 0, 0
2519 …%vuzp.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i3…
2521 %.fca.0.0.insert = insertvalue %struct.uint8x8x2_t undef, <8 x i8> %vuzp.i, 0, 0
2531 %vuzp.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
2533 %.fca.0.0.insert = insertvalue %struct.uint16x4x2_t undef, <4 x i16> %vuzp.i, 0, 0
[all …]
/external/arm-neon-tests/
DMakefile.gcc51 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
DMakefile45 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
Dref_vuzp.c35 #define INSN_NAME vuzp

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