| /external/arm-trusted-firmware/drivers/marvell/ |
| D | ccu.c | 69 uint32_t win_id, win_cr, alr, ahr; in dump_ccu() local
76 for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { in dump_ccu()
77 win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); in dump_ccu()
82 win_id)); in dump_ccu()
84 win_id)); in dump_ccu()
88 win_id, target_id, start, end); in dump_ccu()
114 int ccu_is_win_enabled(int ap_index, uint32_t win_id) in ccu_is_win_enabled() argument
116 return mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)) & in ccu_is_win_enabled()
120 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) in ccu_enable_win() argument
126 if ((win_id == 0) || (win_id > MVEBU_CCU_MAX_WINS)) { in ccu_enable_win()
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| D | io_win.c | 114 uint32_t win_id; in iow_temp_win_insert() local
117 win_id = MVEBU_IO_WIN_MAX_WINS - i - 1; in iow_temp_win_insert()
119 io_win_enable_window(ap_index, win, win_id); in iow_temp_win_insert()
130 uint32_t win_id; in iow_temp_win_remove() local
137 win_id = MVEBU_IO_WIN_MAX_WINS - i - 1; in iow_temp_win_remove()
139 target = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, win_id)); in iow_temp_win_remove()
140 base = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_id)); in iow_temp_win_remove()
146 __func__, win_id); in iow_temp_win_remove()
149 io_win_disable_window(ap_index, win_id); in iow_temp_win_remove()
157 uint32_t trgt_id, win_id; in dump_io_win() local
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| D | iob.c | 69 static void iob_enable_win(struct addr_map_win *win, uint32_t win_id) in iob_enable_win() argument
79 mmio_write_32(IOB_WIN_ALR_OFFSET(win_id), alr); in iob_enable_win()
80 mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr); in iob_enable_win()
85 mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg); in iob_enable_win()
92 uint32_t win_id, win_cr, alr, ahr; in dump_iob() local
102 for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) { in dump_iob()
103 win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); in dump_iob()
107 alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id)); in dump_iob()
109 if (win_id != 0) { in dump_iob()
110 ahr = mmio_read_32(IOB_WIN_AHR_OFFSET(win_id)); in dump_iob()
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| D | amb_adec.c | 96 uint32_t ctrl, base, win_id, attr; in dump_amb_adec() local
102 for (win_id = 0; win_id < AMB_MAX_WIN_ID; win_id++) { in dump_amb_adec()
103 ctrl = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in dump_amb_adec()
105 base = mmio_read_32(AMB_WIN_BASE_OFFSET(win_id)); in dump_amb_adec()
119 uint32_t win_id, win_reg; in init_amb_adec() local
138 for (win_id = 0; win_id < AMB_MAX_WIN_ID; win_id++) { in init_amb_adec()
139 win_reg = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); in init_amb_adec()
141 mmio_write_32(AMB_WIN_CR_OFFSET(win_id), win_reg); in init_amb_adec()
145 for (win_id = 0; win_id < win_count; win_id++, win++) { in init_amb_adec()
146 amb_check_win(win, win_id); in init_amb_adec()
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| D | gwin.c | 109 uint32_t win_id; in gwin_temp_win_insert() local
112 win_id = MVEBU_GWIN_MAX_WINS - i - 1; in gwin_temp_win_insert()
114 gwin_enable_window(ap_index, win, win_id); in gwin_temp_win_insert()
125 uint32_t win_id; in gwin_temp_win_remove() local
131 win_id = MVEBU_GWIN_MAX_WINS - i - 1; in gwin_temp_win_remove()
133 target = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_id)); in gwin_temp_win_remove()
137 base = mmio_read_32(GWIN_ALR_OFFSET(ap_index, win_id)); in gwin_temp_win_remove()
143 __func__, win_id); in gwin_temp_win_remove()
146 gwin_disable_window(ap_index, win_id); in gwin_temp_win_remove()
180 uint32_t win_id; in init_gwin() local
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| /external/arm-trusted-firmware/plat/marvell/armada/a3k/common/ |
| D | dram_win.c | 187 int32_t win_id; in dram_win_map_build() local
192 for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) { in dram_win_map_build()
193 ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); in dram_win_map_build()
202 base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); in dram_win_map_build()
203 size_reg = mmio_read_32(CPU_DEC_WIN_SIZE_REG(win_id)); in dram_win_map_build()
223 static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) in cpu_win_set() argument
228 ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); in cpu_win_set()
230 mmio_write_32(CPU_DEC_WIN_CTRL_REG(win_id), ctrl_reg); in cpu_win_set()
241 mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); in cpu_win_set()
250 mmio_write_32(CPU_DEC_REMAP_LOW_REG(win_id), remap_reg); in cpu_win_set()
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| D | io_addr_dec.c | 36 static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, in set_io_addr_dec_win() argument
56 win_id, dec_win->win_offset), in set_io_addr_dec_win()
59 if (win_id < dec_win->max_remap) in set_io_addr_dec_win()
61 win_id, dec_win->win_offset), base); in set_io_addr_dec_win()
64 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
68 win_id, dec_win->win_offset), ctrl); in set_io_addr_dec_win()
71 win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, in set_io_addr_dec_win()
72 win_id, dec_win->win_offset)), in set_io_addr_dec_win()
74 win_id, dec_win->win_offset))); in set_io_addr_dec_win()
75 if (win_id < dec_win->max_remap) in set_io_addr_dec_win()
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| /external/arm-trusted-firmware/drivers/marvell/mc_trustzone/ |
| D | mc_trustzone.c | 29 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id) in tz_enable_win() argument
34 if ((win_id < 0) || (win_id > MVEBU_TZ_MAX_WINS)) { in tz_enable_win()
35 ERROR("Enabling wrong MC TrustZone window %d!\n", win_id); in tz_enable_win()
46 win_id); in tz_enable_win()
61 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), val); in tz_enable_win()
63 VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id, in tz_enable_win()
64 MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id), in tz_enable_win()
65 mmio_read_32(MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap_index, win_id))); in tz_enable_win()
67 mmio_write_32(MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap_index, win_id), in tz_enable_win()
70 VERBOSE("%s: Win%d[0x%x] configured to 0x%x\n", __func__, win_id, in tz_enable_win()
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| D | mc_trustzone.h | 25 void tz_enable_win(int ap_index, const struct addr_map_win *win, int win_id);
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| /external/arm-trusted-firmware/plat/marvell/armada/a8k/common/mss/ |
| D | mss_bl2_setup.c | 52 int cfg_num, win_id, cfg_idx, cp; in bl2_plat_mmap_init() local
66 for (cfg_idx = 0, win_id = 1; in bl2_plat_mmap_init()
67 (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) { in bl2_plat_mmap_init()
69 if (ccu_is_win_enabled(MVEBU_AP0, win_id)) in bl2_plat_mmap_init()
73 ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id); in bl2_plat_mmap_init()
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| /external/arm-trusted-firmware/plat/marvell/armada/a8k/common/ |
| D | plat_bl31_setup.c | 89 int tz_nr, win_id; in marvell_bl31_security_setup() local
93 for (win_id = 0; win_id < tz_nr; win_id++) in marvell_bl31_security_setup()
94 tz_enable_win(MVEBU_AP0, tz_map, win_id); in marvell_bl31_security_setup()
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| /external/autotest/client/site_tests/power_LoadTest/extension/ |
| D | test.js | 170 setTimeout(function(win_id) { argument
171 record_end_browse_time_for_window(win_id);
172 chrome.windows.remove(win_id);
194 setTimeout(function(cycle, win_id) { argument
196 record_end_browse_time_for_window(win_id);
197 chrome.windows.remove(win_id);
215 function record_end_browse_time_for_window(win_id) { argument
216 chrome.tabs.getAllInWindow(win_id, function(tabs) {
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| /external/arm-trusted-firmware/include/drivers/marvell/ |
| D | ccu.h | 42 void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id);
49 int ccu_is_win_enabled(int ap_index, uint32_t win_id);
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