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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dbitcast-v4f16-v4i16.ll4 ; difficult, so this test has to throw in some llvm.amdgcn.wqm to get them
9 %a_tmp = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %1)
11 %a_i16 = call <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16> %a_i16_tmp)
21 %a_tmp = call <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16> %1)
23 %a_half = call <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half> %a_half_tmp)
30 declare <4 x half> @llvm.amdgcn.wqm.v4f16(<4 x half>) #1
31 declare <4 x i16> @llvm.amdgcn.wqm.v4i16(<4 x i16>) #1
Dllvm.amdgcn.wqm.vote.ll12 %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
22 %w = call i1 @llvm.amdgcn.wqm.vote(i1 true)
32 %w = call i1 @llvm.amdgcn.wqm.vote(i1 false)
50 %w = call i1 @llvm.amdgcn.wqm.vote(i1 %c)
56 declare i1 @llvm.amdgcn.wqm.vote(i1)
Dllvm.amdgcn.kill.ll234 ; GCN-LABEL: {{^}}wqm:
238 define amdgpu_ps void @wqm(float %a) {
240 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)
284 declare i1 @llvm.amdgcn.wqm.vote(i1)
Dwqm.mir1 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
54 # COPY by si-wqm. Ensure the instruction is removed.
Dwqm.ll112 ; Check that WQM is triggered by the wqm intrinsic.
127 %out.0 = call float @llvm.amdgcn.wqm.f32(float %out)
131 ; Check that the wqm intrinsic works correctly for integers.
144 %out.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %out.0)
260 %out.0 = call float @llvm.amdgcn.wqm.f32(float %out)
366 %src0.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %src0.0)
615 ; CHECK-NOT: wqm
839 declare float @llvm.amdgcn.wqm.f32(float) #3
840 declare i32 @llvm.amdgcn.wqm.i32(i32) #3
856 attributes #5 = { "amdgpu-ps-wqm-outputs" }
Datomic_optimizations_pixelshader.ll8 declare i1 @llvm.amdgcn.wqm.vote(i1)
181 %cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
183 %cond2 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
432 %cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
434 %cond2 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
Dspill-m0.ll68 %lds_data = call float @llvm.amdgcn.wqm.f32(float %lds_data_)
190 declare float @llvm.amdgcn.wqm.f32(float) #1
Dllvm.amdgcn.softwqm.ll73 %temp.0 = call float @llvm.amdgcn.wqm.f32(float %temp)
183 declare float @llvm.amdgcn.wqm.f32(float) #3
Dwave32.ll768 %out.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %out.0)
836 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1)
1111 declare i32 @llvm.amdgcn.wqm.i32(i32)
1122 declare i1 @llvm.amdgcn.wqm.vote(i1)
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.wqm.ll12 %ret = call float @llvm.amdgcn.wqm.f32(float %val)
25 %ret = call <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half> %val)
43 %ret = call double @llvm.amdgcn.wqm.f64(double %val)
51 ; %ret = call i1 @llvm.amdgcn.wqm.i1(i1 %vcc)
72 %ret = call <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float> %val)
76 declare i1 @llvm.amdgcn.wqm.i1(i1) #0
77 declare float @llvm.amdgcn.wqm.f32(float) #0
78 declare <2 x half> @llvm.amdgcn.wqm.v2f16(<2 x half>) #0
79 declare <3 x float> @llvm.amdgcn.wqm.v3f32(<3 x float>) #0
80 declare double @llvm.amdgcn.wqm.f64(double) #0
Dllvm.amdgcn.wqm.vote.ll2 …ineinstrs < %S/../llvm.amdgcn.wqm.vote.ll | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE…
3 …ineinstrs < %S/../llvm.amdgcn.wqm.vote.ll | FileCheck -enable-var-scope -check-prefixes=CHECK,WAVE…
Dregbankselect-amdgcn.wqm.vote.mir18 ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY2]](s1)
22 %3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
36 ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[ICMP]](s1)
40 %3:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %2
54 ; CHECK: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), [[COPY1]](s1)
57 %2:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm.vote), %1
Dregbankselect-amdgcn.wqm.mir15 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY1]](s32)
17 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0
29 ; CHECK: [[INT:%[0-9]+]]:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), [[COPY]](s32)
31 %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.wqm), %0
/external/mesa3d/src/amd/compiler/
Daco_insert_exec_mask.cpp57 bool wqm; member
63 wqm(false) in wqm_ctx()
188 if (ctx.loop && ctx.wqm) { in get_block_needs()
199 } else if (ctx.loop && !ctx.wqm) { in get_block_needs()
212 ctx.wqm = false; in get_block_needs()
274 ctx.wqm = true; in get_block_needs()
362 Temp wqm = ctx.info[idx].exec.back().first; in transition_to_Exact() local
364 wqm = bld.sop1(Builder::s_and_saveexec, bld.def(bld.lm), bld.def(s1, scc), in transition_to_Exact()
365 bld.exec(Definition(exact)), ctx.info[idx].exec[0].first, bld.exec(wqm)); in transition_to_Exact()
366 ctx.info[idx].exec.back().first = wqm; in transition_to_Exact()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td3506 int wqm,
3514 let WQM = wqm;
3519 int channels, int wqm> {
3520 def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm,
3523 def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>,
3525 def _V4 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_128, wqm>,
3527 def _V8 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_256, wqm>,
3529 def _V16 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_512, wqm>,
3533 multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> {
3534 defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DMIMGInstructions.td648 multiclass MIMG_Sampler <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
655 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
673 multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
680 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
DSIInstructions.td120 // Pseudoinstruction for @llvm.amdgcn.wqm. It is turned into a copy after the
124 // Pseudoinstruction for @llvm.amdgcn.softwqm. Like @llvm.amdgcn.wqm it is
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader.h582 unsigned wqm : 1; member
Dsi_shader_llvm_ps.c859 if (key->ps_prolog.wqm) { in si_llvm_build_ps_prolog()
Dsi_shader.c2182 key->ps_prolog.wqm = in si_get_ps_prolog_key()
/external/llvm/test/CodeGen/AMDGPU/
Dwqm.ll326 ; CHECK-NOT: wqm
366 attributes #4 = { "amdgpu-ps-wqm-outputs" }
/external/llvm-project/llvm/lib/Target/AMDGPU/
DMIMGInstructions.td664 multiclass MIMG_Sampler <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
672 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
690 multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
697 let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
DSIInstructions.td114 // Pseudoinstruction for @llvm.amdgcn.wqm. It is turned into a copy after the
118 // Pseudoinstruction for @llvm.amdgcn.softwqm. Like @llvm.amdgcn.wqm it is
/external/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/
Damdgcn-intrinsics.ll2448 ; llvm.amdgcn.wqm.vote
2451 declare i1 @llvm.amdgcn.wqm.vote(i1)
2459 %w = call i1 @llvm.amdgcn.wqm.vote(i1 true)
2470 %w = call i1 @llvm.amdgcn.wqm.vote(i1 false)
2481 %w = call i1 @llvm.amdgcn.wqm.vote(i1 undef)
/external/toolchain-utils/android_bench_suite/panorama_input/
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