Home
last modified time | relevance | path

Searched refs:x4 (Results 1 – 25 of 1906) sorted by relevance

12345678910>>...77

/external/libavc/common/armv8/
Dih264_padding_neon_av8.s98 mov x4, x5
103 st1 {v0.8b, v1.8b}, [x4], x6
180 sub x4, x0, x3
192 st1 {v0.16b}, [x4], x1 // 16 bytes store
194 st1 {v2.16b}, [x4], x1 // 16 bytes store
199 st1 {v4.16b}, [x4], x1 // 16 bytes store
202 st1 {v6.16b}, [x4], x1 // 16 bytes store
208 st1 {v0.16b}, [x4], x1 // 16 bytes store
212 st1 {v2.16b}, [x4], x1 // 16 bytes store
216 st1 {v4.16b}, [x4], x1 // 16 bytes store
[all …]
Dih264_default_weighted_pred_av8.s117 sxtw x4, w4
128 ld1 {v2.s}[0], [x1], x4 //load row 1 in source 2
129 ld1 {v2.s}[1], [x1], x4 //load row 2 in source 2
133 ld1 {v3.s}[0], [x1], x4 //load row 3 in source 2
134 ld1 {v3.s}[1], [x1], x4 //load row 4 in source 2
147 ld1 {v4.8b}, [x1], x4 //load row 1 in source 2
149 ld1 {v5.8b}, [x1], x4 //load row 2 in source 2
153 ld1 {v6.8b}, [x1], x4 //load row 3 in source 2
156 ld1 {v7.8b}, [x1], x4 //load row 4 in source 2
169 ld1 {v16.8b, v17.8b}, [x1], x4 //load row 1 in source 2
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfold-frame-offset-using-rr.mir19 liveins: $x3, $x1, $x4, $x6
22 $x4 = ADD8 killed $x3, killed $x4
24 $x6 = LD 4, killed $x4
25 ; CHECK: $x6 = LDX killed $x4, killed $x3
35 liveins: $x3, $x1, $x4, $x6
38 $x3 = ADD8 killed $x3, killed $x4
41 ; CHECK: $x6 = LDX killed $x4, killed $x3
51 liveins: $x3, $x1, $x4, $x6
54 $x3 = ADD8 killed $x3, killed $x4
55 ; CHECK: $x3 = ADD8 killed $x3, killed $x4
[all …]
Dmachine-backward-cp.mir16 renamable $x4 = LI8 1024
17 $x3 = COPY renamable killed $x4
30 ; CHECK: renamable $x4 = LI8 42
33 ; CHECK: liveins: $x4
34 ; CHECK: $x3 = COPY killed renamable $x4
40 renamable $x4 = COPY renamable killed $x5
44 liveins: $x4
45 $x3 = COPY renamable killed $x4
58 ; CHECK: renamable $x4 = LI8 1024
59 ; CHECK: $x13 = COPY killed renamable $x4
[all …]
/external/libaom/libaom/av1/encoder/x86/
Dav1_fwd_txfm_sse2.c132 __m128i x4[8]; in fdct4x8_new_sse2() local
133 x4[0] = x3[0]; in fdct4x8_new_sse2()
134 x4[1] = x3[1]; in fdct4x8_new_sse2()
135 x4[2] = x3[2]; in fdct4x8_new_sse2()
136 x4[3] = x3[3]; in fdct4x8_new_sse2()
138 &x3[7], &x4[4], &x4[7]); in fdct4x8_new_sse2()
140 &x3[6], &x4[5], &x4[6]); in fdct4x8_new_sse2()
143 output[0] = x4[0]; in fdct4x8_new_sse2()
144 output[1] = x4[4]; in fdct4x8_new_sse2()
145 output[2] = x4[2]; in fdct4x8_new_sse2()
[all …]
Dav1_fwd_txfm1d_sse4.c812 __m128i x4[64]; in av1_fdct64_sse4_1() local
813 x4[0] = _mm_add_epi32(x3[0], x3[7]); in av1_fdct64_sse4_1()
814 x4[7] = _mm_sub_epi32(x3[0], x3[7]); in av1_fdct64_sse4_1()
815 x4[1] = _mm_add_epi32(x3[1], x3[6]); in av1_fdct64_sse4_1()
816 x4[6] = _mm_sub_epi32(x3[1], x3[6]); in av1_fdct64_sse4_1()
817 x4[2] = _mm_add_epi32(x3[2], x3[5]); in av1_fdct64_sse4_1()
818 x4[5] = _mm_sub_epi32(x3[2], x3[5]); in av1_fdct64_sse4_1()
819 x4[3] = _mm_add_epi32(x3[3], x3[4]); in av1_fdct64_sse4_1()
820 x4[4] = _mm_sub_epi32(x3[3], x3[4]); in av1_fdct64_sse4_1()
821 x4[8] = x3[8]; in av1_fdct64_sse4_1()
[all …]
/external/llvm-project/clang/test/CodeGen/aarch64-sve-intrinsics/
Dacle_sve_create4.c13 svint8x4_t test_svcreate4_s8(svint8_t x0, svint8_t x1, svint8_t x2, svint8_t x4) in test_svcreate4_s8() argument
18 return SVE_ACLE_FUNC(svcreate4,_s8,,)(x0, x1, x2, x4); in test_svcreate4_s8()
21 svint16x4_t test_svcreate4_s16(svint16_t x0, svint16_t x1, svint16_t x2, svint16_t x4) in test_svcreate4_s16() argument
26 return SVE_ACLE_FUNC(svcreate4,_s16,,)(x0, x1, x2, x4); in test_svcreate4_s16()
29 svint32x4_t test_svcreate4_s32(svint32_t x0, svint32_t x1, svint32_t x2, svint32_t x4) in test_svcreate4_s32() argument
34 return SVE_ACLE_FUNC(svcreate4,_s32,,)(x0, x1, x2, x4); in test_svcreate4_s32()
37 svint64x4_t test_svcreate4_s64(svint64_t x0, svint64_t x1, svint64_t x2, svint64_t x4) in test_svcreate4_s64() argument
42 return SVE_ACLE_FUNC(svcreate4,_s64,,)(x0, x1, x2, x4); in test_svcreate4_s64()
45 svuint8x4_t test_svcreate4_u8(svuint8_t x0, svuint8_t x1, svuint8_t x2, svuint8_t x4) in test_svcreate4_u8() argument
50 return SVE_ACLE_FUNC(svcreate4,_u8,,)(x0, x1, x2, x4); in test_svcreate4_u8()
[all …]
/external/arm-trusted-firmware/plat/arm/board/morello/aarch64/
Dmorello_helper.S34 mov x4, x0
42 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
48 mov x4, #MORELLO_MAX_CLUSTERS_PER_CHIP
49 madd x2, x3, x4, x2
50 mov x4, #MORELLO_MAX_CPUS_PER_CLUSTER
51 madd x1, x2, x4, x1
52 mov x4, #MORELLO_MAX_PE_PER_CPU
[all …]
/external/XNNPACK/scripts/
Dgenerate-f32-dwconv2d-chw.sh8 …n.c.in -D ROW_TILE=1 -D ACCUMULATORS=1 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4.c
9 …n.c.in -D ROW_TILE=2 -D ACCUMULATORS=1 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4.c
10 …n.c.in -D ROW_TILE=3 -D ACCUMULATORS=1 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-3x4.c
11 …n.c.in -D ROW_TILE=4 -D ACCUMULATORS=1 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-4x4.c
12 …n.c.in -D ROW_TILE=5 -D ACCUMULATORS=1 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-5x4.c
13 …n.c.in -D ROW_TILE=6 -D ACCUMULATORS=1 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-6x4.c
15 …n -D ROW_TILE=1 -D ACCUMULATORS=2 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc2.c
16 …n -D ROW_TILE=1 -D ACCUMULATORS=3 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc3.c
17 …n -D ROW_TILE=1 -D ACCUMULATORS=4 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-1x4-acc4.c
18 …n -D ROW_TILE=2 -D ACCUMULATORS=2 -D FMA=0 -o src/f32-dwconv2d-chw/gen/3x3p1-minmax-neon-2x4-acc2.c
[all …]
/external/rust/crates/ppv-lite86/src/
Dsoft.rs201 pub struct x4<W>(pub [W; 4]); struct
202 impl<W> x4<W> { implementation
205 x4(xs)
210 impl<W: $trait + Copy> $trait for x4<W> {
211 type Output = x4<W::Output>;
214 x4([
226 impl<W: $trait + Copy> $trait for x4<W> {
241 x4([
250 impl<W> RotateEachWord32 for x4<W> implementation
263 impl<W> RotateEachWord64 for x4<W> implementation
[all …]
/external/arm-trusted-firmware/plat/arm/board/n1sdp/aarch64/
Dn1sdp_helper.S33 mov x4, x0
41 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
43 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
44 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
47 mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP
48 madd x2, x3, x4, x2
49 mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER
50 madd x1, x2, x4, x1
51 mov x4, #N1SDP_MAX_PE_PER_CPU
[all …]
/external/arm-trusted-firmware/plat/arm/css/sgi/aarch64/
Dsgi_helper.S36 mov x4, x0
44 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
45 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
46 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
47 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
50 mov x4, #PLAT_ARM_CLUSTER_COUNT
51 madd x2, x3, x4, x2
52 mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
53 madd x1, x2, x4, x1
54 mov x4, #CSS_SGI_MAX_PE_PER_CPU
[all …]
/external/libhevc/common/arm64/
Dihevc_padding.s99 sub x4,x0,x3
115 add x5,x4,x1
117 st1 {v0.16b},[x4],#16 //128/8 = 16 bytes store
118 st1 {v0.16b},[x4],#16 // 16 bytes store
119 st1 {v0.16b},[x4],#16 // 16 bytes store
120 st1 {v0.16b},[x4],#16 // 16 bytes store
121 st1 {v0.16b},[x4] // 16 bytes store
217 sub x4,x0,x3
233 add x5,x4,x1
235 st1 {v0.16b},[x4],#16 //128/8 = 16 bytes store
[all …]
Dihevc_inter_pred_filters_luma_horz.s123 mov x15,x4 // pi1_coeff
131 mov x4,x15 //loads pi1_coeff
135 ld1 {v0.8b},[x4] //coeff = vld1_s8(pi1_coeff)
147 add x4,x12,x2 //pu1_src_tmp2_8 = pu1_src + src_strd
198 add x4,x12,x2 //pu1_src + src_strd
236 ld1 {v12.2s},[x4],x11 //vector load pu1_src + src_strd
238 ld1 {v13.2s},[x4],x11
240 ld1 {v14.2s},[x4],x11
242 ld1 {v15.2s},[x4],x11
244 ld1 {v16.2s},[x4],x11 //vector load pu1_src + src_strd
[all …]
/external/boringssl/ios-aarch64/crypto/third_party/sike/asm/
Dfp-armv8.S41 ldp x3, x4, [x0]
52 adcs x4, x4, x8
78 and x21, x4, x8
90 stp x3, x4, [x2,#0]
93 adcs x4, x4, x6
109 and x22, x4, x20
122 mul x3, x4, x23
123 umulh x23, x4, x23
127 mul x24, x4, x26
128 umulh x26, x4, x26
[all …]
/external/llvm-project/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/
Dselects.ll30 %base.x4 = shl i32 %base, 2
31 %base.x4.p1 = add i32 %base.x4, 1
32 %base.x4.p2 = add i32 %base.x4, 2
33 %base.x4.p3 = add i32 %base.x4, 3
34 %zext.x4 = zext i32 %base.x4 to i64
35 %zext.x4.p1 = zext i32 %base.x4.p1 to i64
36 %zext.x4.p2 = zext i32 %base.x4.p2 to i64
37 %zext.x4.p3 = zext i32 %base.x4.p3 to i64
38 %base.x16 = mul i64 %zext.x4, 4
39 %base.x16.p4 = shl i64 %zext.x4.p1, 2
[all …]
/external/llvm/test/MC/AArch64/
Darm64-memory.s8 ldr w5, [x4, #20]
9 ldr x4, [x3]
17 ldrb w5, [x4, #20]
41 prfm pstl3strm, [x4, x5, lsl #3]
43 ; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
44 ; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
52 ; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
75 ; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
81 str x4, [x3]
83 str w5, [x4, #20]
[all …]
/external/llvm-project/llvm/test/MC/AArch64/
Darm64-memory.s8 ldr w5, [x4, #20]
9 ldr x4, [x3]
17 ldrb w5, [x4, #20]
41 prfm pstl3strm, [x4, x5, lsl #3]
43 ; CHECK: ldr w5, [x4, #20] ; encoding: [0x85,0x14,0x40,0xb9]
44 ; CHECK: ldr x4, [x3] ; encoding: [0x64,0x00,0x40,0xf9]
52 ; CHECK: ldrb w5, [x4, #20] ; encoding: [0x85,0x50,0x40,0x39]
75 ; CHECK: prfm pstl3strm, [x4, x5, lsl #3] ; encoding: [0x95,0x78,0xa5,0xf8]
81 str x4, [x3]
83 str w5, [x4, #20]
[all …]
/external/mesa3d/src/amd/addrlib/src/r800/
Dsiaddrlib.cpp231 ADDR_CHANNEL_SETTING x4 = InitChannel(1, 0, log2BytesPP + bankXStart + 1); in ComputeBankEquation() local
240 x4.value = (threshX > bankXStart + 1) ? x4.value : 0; in ComputeBankEquation()
257 pEquation->xor2[1] = x4; in ComputeBankEquation()
269 pEquation->xor2[1] = x4; in ComputeBankEquation()
279 pEquation->addr[1] = x4; in ComputeBankEquation()
291 pEquation->addr[1] = x4; in ComputeBankEquation()
312 pEquation->xor2[1] = x4; in ComputeBankEquation()
322 pEquation->xor2[1] = x4; in ComputeBankEquation()
330 pEquation->addr[1] = x4; in ComputeBankEquation()
348 pEquation->xor1[1] = x4; in ComputeBankEquation()
[all …]
/external/llvm-project/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
19 ; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
20 %res4 = fadd fp128 %x4, %x4
31 define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x…
42 ; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
43 %res4 = fadd <8 x float> %x4, %x4
51 define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, …
62 ; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
63 %res4 = fadd <8 x double> %x4, %x4
71 define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half…
[all …]
DbinaryIntInstructions.3.2.ll8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
19 ; CHECK-NEXT: %res4 = add i32 %x4, %x4
20 %res4 = add i32 %x4, %x4
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
48 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
49 %res4 = add nuw nsw <8 x i8> %x4, %x4
57 define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> …
68 ; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
69 %res4 = add nuw nsw <8 x i16> %x4, %x4
77 define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> …
[all …]
/external/llvm/test/Bitcode/
DbinaryFloatInstructions.3.2.ll8 define void @fadd(float %x1, double %x2 ,half %x3, fp128 %x4, x86_fp80 %x5, ppc_fp128 %x6){
19 ; CHECK-NEXT: %res4 = fadd fp128 %x4, %x4
20 %res4 = fadd fp128 %x4, %x4
31 define void @faddFloatVec(<2 x float> %x1, <3 x float> %x2 ,<4 x float> %x3, <8 x float> %x4, <16 x…
42 ; CHECK-NEXT: %res4 = fadd <8 x float> %x4, %x4
43 %res4 = fadd <8 x float> %x4, %x4
51 define void @faddDoubleVec(<2 x double> %x1, <3 x double> %x2 ,<4 x double> %x3, <8 x double> %x4, …
62 ; CHECK-NEXT: %res4 = fadd <8 x double> %x4, %x4
63 %res4 = fadd <8 x double> %x4, %x4
71 define void @faddHalfVec(<2 x half> %x1, <3 x half> %x2 ,<4 x half> %x3, <8 x half> %x4, <16 x half…
[all …]
/external/libmpeg2/common/armv8/
Dimpeg2_inter_pred.s109 ldr x4, [x0] //src->y
113 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
117 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
119 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
121 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
123 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
125 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
127 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
129 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
131 ld1 {v0.8b, v1.8b}, [x4], x2 //Load and increment src
[all …]
/external/arm-trusted-firmware/common/aarch64/
Ddebug.S41 udiv x0, x4, x5 /* Get the quotient */
42 msub x4, x0, x5, x4 /* Find the remainder */
75 adr x4, assert_msg1
77 mov x4, x5
79 adr x4, assert_msg2
85 mov x4, x6
102 ldrb w0, [x4], #0x1
123 lsrv x0, x4, x5
203 adr x4, panic_msg
205 mov x4, x6
[all …]
/external/pdfium/third_party/agg23/
Dagg_curves.cpp32 float x4, float y4) in init() argument
37 bezier(x1, y1, x2, y2, x3, y3, x4, y4); in init()
43 float x4, float y4, in recursive_bezier() argument
53 float x34 = (x3 + x4) / 2; in recursive_bezier()
61 float dx = x4 - x1; in recursive_bezier()
63 float d2 = fabs(((x2 - x4) * dy) - ((y2 - y4) * dx)); in recursive_bezier()
64 float d3 = fabs(((x3 - x4) * dy) - ((y3 - y4) * dx)); in recursive_bezier()
69 fabs(x2 + x4 - x3 - x3) + fabs(y2 + y4 - y3 - y3) <= in recursive_bezier()
98 recursive_bezier(x1234, y1234, x234, y234, x34, y34, x4, y4, level + 1); in recursive_bezier()
103 float x4, float y4) in bezier() argument
[all …]

12345678910>>...77