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/external/icu/icu4c/source/data/mappings/
Dcns-11643-1992.ucm43 <subchar> \x81\x7e\x7e
58 <U0020> \x81\x21\x21 |0
59 <U0021> \x81\x21\x2A |0
60 <U0023> \x81\x21\x6C |0
61 <U0024> \x81\x22\x63 |0
62 <U0025> \x81\x22\x68 |0
63 <U0026> \x81\x21\x6D |0
64 <U0028> \x81\x21\x3E |0
65 <U0029> \x81\x21\x3F |0
66 <U002B> \x81\x22\x30 |0
[all …]
Dgb18030.ucm187 <U0080> \x81\x30\x81\x30 |0
188 <U0081> \x81\x30\x81\x31 |0
189 <U0082> \x81\x30\x81\x32 |0
190 <U0083> \x81\x30\x81\x33 |0
191 <U0084> \x81\x30\x81\x34 |0
192 <U0085> \x81\x30\x81\x35 |0
193 <U0086> \x81\x30\x81\x36 |0
194 <U0087> \x81\x30\x81\x37 |0
195 <U0088> \x81\x30\x81\x38 |0
196 <U0089> \x81\x30\x81\x39 |0
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt3 # VI: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
4 0x02 0x00 0x81 0xbe
6 # VI: s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]
7 0x81 0x00 0x81 0xbe
9 # VI: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x00,0x81,0xbe,0x64,0x00,0x00,0x00]
10 0xff 0x00 0x81 0xbe 0x64 0x00 0x00 0x00
12 # VI: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x00,0x81,0xbe,0x00,0x00,0x00,0x80]
13 0xff 0x00 0x81 0xbe 0x00 0x00 0x00 0x80
30 # VI: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x02,0x81,0xbe,0xc8,0x00,0x00,0x00]
31 0xff 0x02 0x81 0xbe 0xc8 0x00 0x00 0x00
[all …]
Dmubuf_vi.txt15 …r_load_dword v1, off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x81,0x01]
16 0x04 0x00 0x50 0xe0 0x00 0x01 0x81 0x01
18 …buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x81,0x01]
19 0x00 0x40 0x50 0xe0 0x00 0x01 0x81 0x01
21 …word v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]
22 0x04 0x40 0x52 0xe0 0x00 0x01 0x81 0x01
36 …d_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x50,0xe0,0x02,0x01,0x81,0x01]
37 0x04 0x10 0x50 0xe0 0x02 0x01 0x81 0x01
39 …r_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x50,0xe0,0x02,0x01,0x81,0x01]
40 0x00 0x50 0x50 0xe0 0x02 0x01 0x81 0x01
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt3 # VI: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
4 0x02 0x00 0x81 0xbe
6 # VI: s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]
7 0x81 0x00 0x81 0xbe
9 # VI: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x00,0x81,0xbe,0x64,0x00,0x00,0x00]
10 0xff 0x00 0x81 0xbe 0x64 0x00 0x00 0x00
12 # VI: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x00,0x81,0xbe,0x00,0x00,0x00,0x80]
13 0xff 0x00 0x81 0xbe 0x00 0x00 0x00 0x80
39 # VI: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x02,0x81,0xbe,0xc8,0x00,0x00,0x00]
40 0xff 0x02 0x81 0xbe 0xc8 0x00 0x00 0x00
[all …]
Dmubuf_vi.txt15 …r_load_dword v1, off, s[4:7], s1 offset:4 tfe ; encoding: [0x04,0x00,0x50,0xe0,0x00,0x01,0x81,0x01]
16 0x04 0x00 0x50 0xe0 0x00 0x01 0x81 0x01
18 …buffer_load_dword v1, off, s[4:7], s1 glc tfe ; encoding: [0x00,0x40,0x50,0xe0,0x00,0x01,0x81,0x01]
19 0x00 0x40 0x50 0xe0 0x00 0x01 0x81 0x01
21 …word v1, off, s[4:7], s1 offset:4 glc slc tfe ; encoding: [0x04,0x40,0x52,0xe0,0x00,0x01,0x81,0x01]
22 0x04 0x40 0x52 0xe0 0x00 0x01 0x81 0x01
36 …d_dword v1, v2, s[4:7], s1 offen offset:4 tfe ; encoding: [0x04,0x10,0x50,0xe0,0x02,0x01,0x81,0x01]
37 0x04 0x10 0x50 0xe0 0x02 0x01 0x81 0x01
39 …r_load_dword v1, v2, s[4:7], s1 offen glc tfe ; encoding: [0x00,0x50,0x50,0xe0,0x02,0x01,0x81,0x01]
40 0x00 0x50 0x50 0xe0 0x02 0x01 0x81 0x01
[all …]
Dliteral_gfx9.txt6 # GFX9: s_add_i32 s0, src_shared_base, s0 ; encoding: [0xeb,0x00,0x00,0x81]
7 0xeb,0x00,0x00,0x81
9 # GFX9: s_add_i32 s0, src_shared_limit, s0 ; encoding: [0xec,0x00,0x00,0x81]
10 0xec,0x00,0x00,0x81
12 # GFX9: s_add_i32 s0, src_private_base, s0 ; encoding: [0xed,0x00,0x00,0x81]
13 0xed,0x00,0x00,0x81
15 # GFX9: s_add_i32 s0, src_private_limit, s0 ; encoding: [0xee,0x00,0x00,0x81]
16 0xee,0x00,0x00,0x81
18 # GFX9: s_add_i32 s0, src_pops_exiting_wave_id, s0 ; encoding: [0xef,0x00,0x00,0x81]
19 0xef,0x00,0x00,0x81
[all …]
Dsmem_gfx9.txt16 # GFX9: s_scratch_load_dwordx2 s[10:11], s[2:3], 0x1 glc ; encoding: [0x81,0x02,0x1b,0xc0,0x01,0x00…
17 0x81,0x02,0x1b,0xc0,0x01,0x00,0x00,0x00
57 # GFX9: s_atomic_add_x2 s[10:11], s[2:3], s101 ; encoding: [0x81,0x02,0x88,0xc2,0x65,0x00,0x00,0…
58 0x81,0x02,0x88,0xc2,0x65,0x00,0x00,0x00
66 # GFX9: s_atomic_cmpswap s[10:11], s[2:3], s101 ; encoding: [0x81,0x02,0x04,0xc2,0x65,0x00,0x00,…
67 0x81,0x02,0x04,0xc2,0x65,0x00,0x00,0x00
69 # GFX9: s_atomic_cmpswap s[10:11], s[2:3], 0x0 ; encoding: [0x81,0x02,0x06,0xc2,0x00,0x00,0x00,0…
70 0x81,0x02,0x06,0xc2,0x00,0x00,0x00,0x00
72 # GFX9: s_atomic_cmpswap s[10:11], s[2:3], s0 glc ; encoding: [0x81,0x02,0x05,0xc2,0x00,0x00,0x0…
73 0x81,0x02,0x05,0xc2,0x00,0x00,0x00,0x00
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.setreg.ll21 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
28 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
35 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
45 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x0…
48 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
52 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x00,0xba,0…
55 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
59 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x…
62 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
72 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x0…
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.s.setreg.ll21 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
28 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
35 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
45 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x0…
48 ; GFX6-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
52 ; GFX789-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x00,0xba,0…
55 ; GFX789-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
59 ; GFX10-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 3 ; encoding: [0x81,0x08,0x80,0xba,0x…
62 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
72 ; GFX6-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 4), 7 ; encoding: [0x81,0x18,0x80,0xba,0x0…
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/AArch64/
Darmv8.4a-tlb.txt6 0x1f,0x81,0x08,0xd5
7 0x20,0x81,0x08,0xd5
8 0x40,0x81,0x08,0xd5
9 0x60,0x81,0x08,0xd5
10 0xa0,0x81,0x08,0xd5
11 0xe0,0x81,0x08,0xd5
14 0x20,0x81,0x0c,0xd5
15 0xa0,0x81,0x0c,0xd5
16 0xdf,0x81,0x0c,0xd5
17 0x20,0x81,0x0e,0xd5
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont-VST-reencoding.txt4 0x81 0xf9 0x21 0x10
5 0x81 0xf9 0x42 0x10
6 0x81 0xf9 0x61 0x20
13 # CHECK: vst1.8 {d1[1]}, [r1], r1 @ encoding: [0x81,0xf9,0x21,0x10]
14 # CHECK: vst1.8 {d1[2]}, [r1], r2 @ encoding: [0x81,0xf9,0x42,0x10]
15 # CHECK: vst1.8 {d2[3]}, [r1], r1 @ encoding: [0x81,0xf9,0x61,0x20]
49 0x81 0xf9 0x1f 0x44
52 # CHECK: vst1.16 {d4[0]}, [r1:16] @ encoding: [0x81,0xf9,0x1f,0x44]
71 0x81 0xf9 0x24 0x0b
75 # CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1:128], r4 @ encoding: [0x81,0xf9,0x24,0x0b]
Dmove-banked-regs-thumb.txt8 [0xe5,0xf3,0x20,0x81]
23 [0xed,0xf3,0x20,0x81]
37 [0xf0,0xf3,0x30,0x81]
42 [0xe2,0xf3,0x30,0x81]
81 [0x83,0xf3,0x20,0x81]
85 [0x81,0xf3,0x20,0x85]
100 [0x81,0xf3,0x20,0x8d]
113 [0x89,0xf3,0x30,0x81]
119 [0x81,0xf3,0x30,0x82]
Dfullfp16-neon-thumb-neg.txt154 [0xb7,0xff,0x81,0x05]
164 [0xb5,0xff,0x81,0x07]
176 [0xb7,0xff,0x81,0x07]
178 [0xb7,0xff,0x81,0x06]
190 [0xb7,0xff,0x81,0x00]
199 [0xb7,0xff,0x81,0x03]
208 [0xb7,0xff,0x81,0x01]
217 [0xb7,0xff,0x81,0x02]
244 [0xb6,0xff,0x81,0x06]
254 [0xb6,0xff,0x81,0x07]
[all …]
Dfullfp16-neon-arm-neg.txt154 [0x81,0x05,0xb7,0xf3]
164 [0x81,0x07,0xb5,0xf3]
176 [0x81,0x07,0xb7,0xf3]
178 [0x81,0x06,0xb7,0xf3]
190 [0x81,0x00,0xb7,0xf3]
199 [0x81,0x03,0xb7,0xf3]
208 [0x81,0x01,0xb7,0xf3]
217 [0x81,0x02,0xb7,0xf3]
244 [0x81,0x06,0xb6,0xf3]
254 [0x81,0x07,0xb6,0xf3]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dneont-VST-reencoding.txt4 0x81 0xf9 0x21 0x10
5 0x81 0xf9 0x42 0x10
6 0x81 0xf9 0x61 0x20
13 # CHECK: vst1.8 {d1[1]}, [r1], r1 @ encoding: [0x81,0xf9,0x21,0x10]
14 # CHECK: vst1.8 {d1[2]}, [r1], r2 @ encoding: [0x81,0xf9,0x42,0x10]
15 # CHECK: vst1.8 {d2[3]}, [r1], r1 @ encoding: [0x81,0xf9,0x61,0x20]
49 0x81 0xf9 0x1f 0x44
52 # CHECK: vst1.16 {d4[0]}, [r1:16] @ encoding: [0x81,0xf9,0x1f,0x44]
71 0x81 0xf9 0x24 0x0b
75 # CHECK: vst4.32 {d0[0], d1[0], d2[0], d3[0]}, [r1:128], r4 @ encoding: [0x81,0xf9,0x24,0x0b]
Dmove-banked-regs-thumb.txt8 [0xe5,0xf3,0x20,0x81]
23 [0xed,0xf3,0x20,0x81]
37 [0xf0,0xf3,0x30,0x81]
42 [0xe2,0xf3,0x30,0x81]
81 [0x83,0xf3,0x20,0x81]
85 [0x81,0xf3,0x20,0x85]
100 [0x81,0xf3,0x20,0x8d]
113 [0x89,0xf3,0x30,0x81]
119 [0x81,0xf3,0x30,0x82]
Dfullfp16-neon-arm-neg.txt154 [0x81,0x05,0xb7,0xf3]
164 [0x81,0x07,0xb5,0xf3]
176 [0x81,0x07,0xb7,0xf3]
178 [0x81,0x06,0xb7,0xf3]
190 [0x81,0x00,0xb7,0xf3]
199 [0x81,0x03,0xb7,0xf3]
208 [0x81,0x01,0xb7,0xf3]
217 [0x81,0x02,0xb7,0xf3]
244 [0x81,0x06,0xb6,0xf3]
254 [0x81,0x07,0xb6,0xf3]
[all …]
Dfullfp16-neon-thumb-neg.txt154 [0xb7,0xff,0x81,0x05]
164 [0xb5,0xff,0x81,0x07]
176 [0xb7,0xff,0x81,0x07]
178 [0xb7,0xff,0x81,0x06]
190 [0xb7,0xff,0x81,0x00]
199 [0xb7,0xff,0x81,0x03]
208 [0xb7,0xff,0x81,0x01]
217 [0xb7,0xff,0x81,0x02]
244 [0xb6,0xff,0x81,0x06]
254 [0xb6,0xff,0x81,0x07]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/Sparc/
Dsparc-special-registers.txt4 0x81 0x80 0x7f 0xfe
13 0x81 0x86 0x20 0x05
28 0x81 0x8e 0x20 0x05
31 0x81 0x96 0x20 0x05
34 0x81 0x9e 0x20 0x05
Dsparc-v9.txt19 0x81 0xd0 0x00 0x1d
76 0x81 0xd0 0x10 0x1d
121 0x81 0x43 0xf3 0x88
124 0x81 0x43 0xe0 0x0f
127 0x81 0x43 0xe0 0x01
130 0x81 0x43 0xe0 0x09
133 0x81 0x43 0xe0 0x7f
/external/llvm/test/MC/Disassembler/Sparc/
Dsparc-special-registers.txt4 0x81 0x80 0x7f 0xfe
13 0x81 0x86 0x20 0x05
28 0x81 0x8e 0x20 0x05
31 0x81 0x96 0x20 0x05
34 0x81 0x9e 0x20 0x05
/external/skqp/src/compute/hs/cl/intel/gen8/u32/
Dhs_kernels.bin.xxd56 0x00, 0x07, 0x81, 0x23, 0x91, 0x41, 0xc8, 0x04, 0x49, 0x06, 0x10, 0x32,
61 0x90, 0x11, 0x23, 0xc4, 0x50, 0x41, 0x51, 0x81, 0x8c, 0xe1, 0x83, 0xe5,
65 0x41, 0x1e, 0xe4, 0xa1, 0x1c, 0xc6, 0x81, 0x1e, 0xd8, 0x21, 0x1f, 0xda,
66 0x40, 0x1e, 0xde, 0xa1, 0x1e, 0xdc, 0x81, 0x1c, 0xca, 0x81, 0x1c, 0xda,
67 0x80, 0x1c, 0xd2, 0xc1, 0x1e, 0xd2, 0x81, 0x1c, 0xca, 0xa1, 0x0d, 0xe6,
68 0x21, 0x1e, 0xe4, 0x81, 0x1e, 0xda, 0xc0, 0x1c, 0xe0, 0xa1, 0x0d, 0xda,
72 0x70, 0x60, 0x07, 0x76, 0x98, 0x07, 0xc0, 0x1c, 0xc2, 0x81, 0x1d, 0xe6,
81 0xa0, 0x1d, 0xc2, 0x81, 0x1e, 0xd0, 0x01, 0xa0, 0x07, 0x79, 0xa8, 0x87,
84 0xc0, 0x1c, 0xc2, 0x81, 0x1d, 0xe6, 0xa1, 0x1c, 0x00, 0xc2, 0x1d, 0xde,
114 0xc8, 0x43, 0x39, 0x8c, 0x43, 0x3a, 0xcc, 0x43, 0x39, 0xb4, 0x81, 0x39,
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dspecial-reg-mcore.ll12 ; MCORE: mrs r1, iapsr @ encoding: [0xef,0xf3,0x01,0x81]
13 ; MCORE: mrs r1, eapsr @ encoding: [0xef,0xf3,0x02,0x81]
14 ; MCORE: mrs r1, xpsr @ encoding: [0xef,0xf3,0x03,0x81]
15 ; MCORE: mrs r1, ipsr @ encoding: [0xef,0xf3,0x05,0x81]
16 ; MCORE: mrs r1, epsr @ encoding: [0xef,0xf3,0x06,0x81]
17 ; MCORE: mrs r1, iepsr @ encoding: [0xef,0xf3,0x07,0x81]
18 ; MCORE: mrs r1, msp @ encoding: [0xef,0xf3,0x08,0x81]
19 ; MCORE: mrs r1, psp @ encoding: [0xef,0xf3,0x09,0x81]
20 ; MCORE: mrs r1, primask @ encoding: [0xef,0xf3,0x10,0x81]
21 ; MCORE: mrs r1, basepri @ encoding: [0xef,0xf3,0x11,0x81]
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARC/
Dalu.txt25 0x04 0x27 0x02 0x81
37 0x40 0x29 0x81 0x00
55 0x02 0x29 0x81 0x00
76 0x05 0x21 0x81 0x03
91 0x02 0x27 0x02 0x81

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