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Searched refs:xreg (Results 1 – 6 of 6) sorted by relevance

/external/vixl/test/aarch64/examples/
Dtest-examples.cc193 VIXL_CHECK(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
218 VIXL_CHECK(static_cast<uint64_t>(regs.xreg(0)) == FactorialC(N)); \
401 VIXL_CHECK(regs.xreg(0) == SumArrayC(Array, ARRAY_SIZE(Array))); \
429 VIXL_CHECK(regs.xreg(0) == abs(X)); \
462 VIXL_CHECK(regs.xreg(0) == chksum); in TEST()
484 VIXL_CHECK(regs.xreg(0) == d); in TEST()
485 VIXL_CHECK(regs.xreg(1) == c); in TEST()
486 VIXL_CHECK(regs.xreg(2) == b); in TEST()
487 VIXL_CHECK(regs.xreg(3) == a); in TEST()
516 VIXL_CHECK(regs.xreg(0) == ((Low <= Value) && (Value <= High))); \
[all …]
/external/vixl/test/aarch64/
Dtest-utils-aarch64.cc179 int64_t result_x = core->xreg(reg.GetCode()); in Equal32()
196 uint64_t result = core->xreg(reg.GetCode()); in Equal64()
205 uint64_t result = core->xreg(reg.GetCode()); in NotEqual64()
273 int64_t reference = core->xreg(reg0.GetCode()); in Equal64()
274 int64_t result = core->xreg(reg1.GetCode()); in Equal64()
283 int64_t expected = core->xreg(reg0.GetCode()); in NotEqual64()
284 int64_t result = core->xreg(reg1.GetCode()); in NotEqual64()
332 if (a->xreg(i) != b->xreg(i)) { in EqualRegisters()
335 a->xreg(i), in EqualRegisters()
336 b->xreg(i)); in EqualRegisters()
Dtest-utils-aarch64.h125 inline int64_t xreg(unsigned code) const { in xreg() function
Dtest-assembler-sve-aarch64.cc9031 uintptr_t measured_limit = core.xreg(limit.GetCode()); in Ldff1Helper()
9608 int64_t loaded_data_in_bytes = core.xreg(x10.GetCode()); in TEST_SVE()
/external/llvm-project/lldb/source/Plugins/Process/Utility/
DRegisterInfos_arm64.h497 #define DEFINE_GPR32(wreg, xreg) \ argument
500 GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET, \
502 g_contained_##xreg, g_##wreg##_invalidates, nullptr, 0 \
/external/vixl/src/aarch64/
Dsimulator-aarch64.h1221 int64_t xreg(unsigned code,