Searched refs:zbs (Results 1 – 17 of 17) sorted by relevance
| /external/llvm-project/llvm/test/MC/RISCV/ |
| D | rv64zbs-valid.s | 9 # RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zbs -show-encoding \
11 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zbs < %s \
12 # RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
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| D | rv32zbs-valid.s | 9 # RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zbs -show-encoding \
11 # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zbs < %s \
12 # RUN: | llvm-objdump --mattr=+experimental-zbs -d -r - \
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| D | rv64zbs-invalid.s | 1 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s
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| D | rv32zbs-invalid.s | 1 # RUN: not llvm-mc -triple riscv32 -mattr=+experimental-b,experimental-zbs < %s 2>&1 | FileCheck %s
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_context.h | 317 struct radeon_state_atom zbs; member
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| D | radeon_context.c | 99 rmesa->hw.zbs.dirty = 1; in r100_vtbl_pre_emit_state()
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| D | radeon_ioctl.c | 81 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs); in radeonSetUpAtomList()
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| D | radeon_state_init.c | 546 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); in radeonInitState()
617 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); in radeonInitState()
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| D | radeon_state.c | 529 RADEON_STATECHANGE( rmesa, zbs ); in radeonPolygonOffset()
530 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR] = factoru.ui32; in radeonPolygonOffset()
531 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32; in radeonPolygonOffset()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_context.h | 495 struct radeon_state_atom zbs; member
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| D | r200_cmdbuf.c | 74 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs ); in r200SetUpAtomList()
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| D | r200_state.c | 729 R200_STATECHANGE( rmesa, zbs ); in r200PolygonOffset()
730 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_FACTOR] = factoru.ui32; in r200PolygonOffset()
731 rmesa->hw.zbs.cmd[ZBS_SE_ZBIAS_CONSTANT] = constant.ui32; in r200PolygonOffset()
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| D | r200_state_init.c | 663 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 ); in r200InitState()
808 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR); in r200InitState()
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| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCV.td | 109 : SubtargetFeature<"experimental-zbs", "HasStdExtZbs", "true",
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| /external/llvm-project/llvm/test/CodeGen/RISCV/ |
| D | rv32Zbs.ll | 6 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs -verify-machineinstrs < %s \
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| D | rv64Zbs.ll | 6 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs -verify-machineinstrs < %s \
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| /external/cldr/tools/java/org/unicode/cldr/util/data/transforms/ |
| D | internal_raw_IPA-old.txt | 217171 zbs %11545
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