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Searched refs:reg (Results 1 – 9 of 9) sorted by relevance

/tools/dexter/slicer/
Dinstrumentation.cc185 dex::u4 reg = regs - ins_count; in GenerateShiftParamsCode() local
191 move->operands.push_back(code_ir->Alloc<lir::VReg>(reg - shift)); in GenerateShiftParamsCode()
192 move->operands.push_back(code_ir->Alloc<lir::VReg>(reg)); in GenerateShiftParamsCode()
193 reg += 1; in GenerateShiftParamsCode()
197 move->operands.push_back(code_ir->Alloc<lir::VReg>(reg - shift)); in GenerateShiftParamsCode()
198 move->operands.push_back(code_ir->Alloc<lir::VReg>(reg)); in GenerateShiftParamsCode()
199 reg += 1; in GenerateShiftParamsCode()
203 move->operands.push_back(code_ir->Alloc<lir::VRegPair>(reg - shift)); in GenerateShiftParamsCode()
204 move->operands.push_back(code_ir->Alloc<lir::VRegPair>(reg)); in GenerateShiftParamsCode()
205 reg += 2; in GenerateShiftParamsCode()
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Ddebuginfo_encoder.cc72 auto reg = dbg_annotation->CastOperand<VReg>(0)->reg; in Visit() local
76 dbginfo_.PushULeb128(reg); in Visit()
82 auto reg = dbg_annotation->CastOperand<VReg>(0)->reg; in Visit() local
87 dbginfo_.PushULeb128(reg); in Visit()
95 auto reg = dbg_annotation->CastOperand<VReg>(0)->reg; in Visit() local
97 dbginfo_.PushULeb128(reg); in Visit()
Dbytecode_encoder.cc99 : bytecode->CastOperand<VReg>(index)->reg; in GetRegA()
108 : bytecode->CastOperand<VReg>(index)->reg; in GetRegB()
117 : bytecode->CastOperand<VReg>(index)->reg; in GetRegC()
/tools/dexter/dexter/
Dexperimental.cc234 dex::u4 reg = 0; in StressExitHook() local
244 reg = bytecode->CastOperand<lir::VReg>(0)->reg; in StressExitHook()
250 reg = bytecode->CastOperand<lir::VReg>(0)->reg; in StressExitHook()
256 reg = bytecode->CastOperand<lir::VRegPair>(0)->base_reg; in StressExitHook()
265 auto args = code_ir.Alloc<lir::VRegRange>(reg, reg_count); in StressExitHook()
Ddissasembler.cc134 printf("v%d", vreg->reg); in Visit()
146 for (auto reg : vreg_list->registers) { in Visit() local
147 printf("%sv%d", (first ? "" : ","), reg); in Visit()
/tools/dexter/slicer/export/slicer/
Dcode_ir.h152 dex::u4 reg; member
154 explicit VReg(dex::u4 reg) : reg(reg) {} in VReg()
/tools/asuite/atest-py2/test_runners/
Drobolectric_test_runner.py164 reg = re.compile(r'(.|\n)*}\n\n')
165 if not reg.match(buf) or data == '':
/tools/asuite/atest/test_runners/
Drobolectric_test_runner.py175 reg = re.compile(r'(.|\n)*}\n\n')
176 if not reg.match(buf) or data == '':
/tools/asuite/atest/
Datest_utils.py890 reg = ('^((0[1-9])|(1[0-2]))-((0[1-9])|([12][0-9])|(3[0-1])) '
892 if re.search(reg, content):