| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 86 unsigned &BaseReg, in findSRegBaseAndIndex()
175 unsigned BaseReg = 0; in fixupGlobalSaddr() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 314 unsigned BaseReg, in isFrameOffsetLegal()
325 unsigned BaseReg, in materializeFrameBaseRegister()
346 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | AArch64StorePairSuppress.cpp | 146 unsigned BaseReg; in runOnMachineFunction() local
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| D | AArch64LoadStoreOptimizer.cpp | 1104 unsigned BaseReg = getLdStBaseOp(LoadMI).getReg(); in findMatchingStore() local
1217 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1422 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1480 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1534 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 287 Register BaseReg = Ldst->getOperand(BasePos).getReg(); in canJoinInstructions() local
343 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses()
449 Register BaseReg = Ldst.getOperand(BasePos).getReg(); in changeToAddrMode() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 398 unsigned BaseReg, in isFrameOffsetLegal()
408 unsigned BaseReg, in materializeFrameBaseRegister()
429 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | AArch64StorePairSuppress.cpp | 154 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
189 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
430 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
188 Register BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
429 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| D | Thumb2SizeReduction.cpp | 499 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
529 Register BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
537 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
550 Register BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
326 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 123 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg() local
272 unsigned BaseReg, in materializeFrameBaseRegister()
303 void SIRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
362 unsigned BaseReg, in isFrameOffsetLegal()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 524 Register BaseReg, in isFrameOffsetLegal()
534 Register BaseReg, in materializeFrameBaseRegister()
555 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, Register BaseReg, in resolveFrameIndex()
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| D | AArch64FalkorHWPFFix.cpp | 217 Register BaseReg; member
646 Register BaseReg = MI.getOperand(BaseRegIdx).getReg(); in getLoadInfo() local
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| D | AArch64StorePairSuppress.cpp | 156 Register BaseReg = BaseOp->getReg(); in runOnMachineFunction() local
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 125 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg()
181 unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmediate()
421 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCTargetDesc.h | 51 auto BaseReg = MI.getOperand(0).getReg(); in isLDMBaseRegInList() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 269 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
343 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 271 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
345 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
206 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
225 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
358 unsigned BaseReg = Base.getReg(); in emitMemModRMByte() local
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 231 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference() local
296 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 285 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference() local
350 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference() local
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| /external/llvm-project/llvm/tools/llvm-exegesis/lib/X86/ |
| D | Target.cpp | 253 for (const unsigned BaseReg : PossibleBaseRegs.set_bits()) { in generateLEATemplatesCommon() local
318 BitVector &CandidateDestRegs) { in generateCodeTemplates()
378 BitVector &CandidateDestRegs) { in generateCodeTemplates()
|