| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1134 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1155 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1187 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1203 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1259 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1298 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1353 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1383 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
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| D | AArch64ISelLowering.cpp | 9229 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1244 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1361 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1387 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1443 void AArch64DAGToDAGISel::SelectPredicatedLoad(SDNode *N, unsigned NumVecs, in SelectPredicatedLoad()
1476 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1496 void AArch64DAGToDAGISel::SelectPredicatedStore(SDNode *N, unsigned NumVecs, in SelectPredicatedStore()
1538 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1594 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1633 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1688 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
[all …]
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| D | AArch64ISelLowering.cpp | 14140 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
15491 uint64_t NumVecs = TupleLanes / NumLanes; in PerformDAGCombine() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1164 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1279 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1305 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1337 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1357 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1413 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1452 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1507 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1536 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
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| D | AArch64ISelLowering.cpp | 11657 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 669 unsigned NumVecs) { in createInterleaveMask()
727 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
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| /external/llvm-project/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 783 unsigned NumVecs) { in createInterleaveMask()
842 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
1808 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1944 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2093 unsigned NumVecs, in SelectVLDSTLane()
2214 void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLDDup()
2296 void ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, in SelectVTBL()
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| D | ARMISelLowering.cpp | 9923 unsigned NumVecs = 0; in CombineBaseUpdate() local
10123 unsigned NumVecs = 0; in CombineVLDDUP() local
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1915 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
2050 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
2055 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
2197 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2352 unsigned NumVecs, in SelectVLDSTLane()
2730 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD()
2891 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
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| D | ARMISelLowering.cpp | 14067 unsigned NumVecs = 0; in CombineBaseUpdate() local
14303 unsigned NumVecs = 0; in PerformMVEVLDCombine() local
14396 unsigned NumVecs = 0; in CombineVLDDUP() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1868 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
2003 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement()
2008 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
2147 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2299 unsigned NumVecs, in SelectVLDSTLane()
2646 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs, in SelectMVE_VLD()
2688 bool isUpdating, unsigned NumVecs, in SelectVLDDup()
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| D | ARMISelLowering.cpp | 13107 unsigned NumVecs = 0; in CombineBaseUpdate() local
13311 unsigned NumVecs = 0; in CombineVLDDUP() local
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10578 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
10801 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
10846 unsigned NumVecs = 2; in LowerVectorStore() local
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| /external/llvm-project/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 14856 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 30142 unsigned NumVecs = VT.getSizeInBits() / 128; in combineToExtendVectorInReg() local
|