| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 598 bool isAdd = true; in EncodeAddrModeOpValues() local
979 bool isAdd = true; in getAddrModeImm12OpValue() local
1036 bool isAdd = Imm >= 0; in getT2ScaledImmOpValue() local
1085 bool isAdd = Imm >= 0; in getMveAddrModeQOpValue() local
1112 bool isAdd = true; in getT2AddrModeImm8s4OpValue() local
1154 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI); in getT2AddrModeImm7s4OpValue() local
1251 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue() local
1285 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; in getAddrMode2OffsetOpValue() local
1306 bool isAdd = MO1.getImm() != 0; in getPostIdxRegOpValue() local
1321 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; in getAddrMode3OffsetOpValue() local
[all …]
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| D | ARMAsmBackend.cpp | 492 bool isAdd = true; in adjustFixupValue() local
721 bool isAdd = true; in adjustFixupValue() local
741 bool isAdd = true; in adjustFixupValue() local
768 bool isAdd = true; in adjustFixupValue() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 606 bool isAdd = true; in EncodeAddrModeOpValues() local
987 bool isAdd = true; in getAddrModeImm12OpValue() local
1044 bool isAdd = Imm >= 0; in getT2ScaledImmOpValue() local
1093 bool isAdd = Imm >= 0; in getMveAddrModeQOpValue() local
1120 bool isAdd = true; in getT2AddrModeImm8s4OpValue() local
1162 bool isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm7, Fixups, STI); in getT2AddrModeImm7s4OpValue() local
1259 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue() local
1293 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; in getAddrMode2OffsetOpValue() local
1314 bool isAdd = MO1.getImm() != 0; in getPostIdxRegOpValue() local
1329 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; in getAddrMode3OffsetOpValue() local
[all …]
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| D | ARMAsmBackend.cpp | 485 bool isAdd = true; in adjustFixupValue() local
714 bool isAdd = true; in adjustFixupValue() local
734 bool isAdd = true; in adjustFixupValue() local
761 bool isAdd = true; in adjustFixupValue() local
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 560 bool isAdd = true; in EncodeAddrModeOpValues() local
879 bool isAdd = true; in getAddrModeImm12OpValue() local
937 bool isAdd = Imm8 >= 0; in getT2Imm8s4OpValue() local
963 bool isAdd = true; in getT2AddrModeImm8s4OpValue() local
1075 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue() local
1109 bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add; in getAddrMode2OffsetOpValue() local
1130 bool isAdd = MO1.getImm() != 0; in getPostIdxRegOpValue() local
1145 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; in getAddrMode3OffsetOpValue() local
1181 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add; in getAddrMode3OpValue() local
1241 bool isAdd; in getAddrMode5OpValue() local
[all …]
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| D | ARMAsmBackend.cpp | 410 bool isAdd = true; in adjustFixupValue() local
610 bool isAdd = true; in adjustFixupValue() local
630 bool isAdd = true; in adjustFixupValue() local
657 bool isAdd = true; in adjustFixupValue() local
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| /external/apache-commons-math/src/main/java/org/apache/commons/math/fraction/ |
| D | Fraction.java | 476 private Fraction addSub(Fraction fraction, boolean isAdd) { in addSub()
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| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 262 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 277 bool isAdd() const { return Flags & (1ULL << MCID::Add); } in isAdd() function
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 248 bool isAdd : 1; variable
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 421 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in findInductionRegister() local
1602 bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); in fixupInductionVariable() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 524 bool isAdd; member
2392 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
2403 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
4647 bool isAdd = true; in parsePostIdxReg() local
4729 bool isAdd = true; in parseAM3Offset() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 795 bool isAdd; member
3095 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3106 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3644 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
5441 bool isAdd = true; in parsePostIdxReg() local
5523 bool isAdd = true; in parseAM3Offset() local
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| /external/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 861 bool isAdd; member
3161 bool isAdd = Imm >= 0; in addPostIdxImm8Operands() local
3172 bool isAdd = Imm >= 0; in addPostIdxImm8s4Operands() local
3709 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
5514 bool isAdd = true; in parsePostIdxReg() local
5596 bool isAdd = true; in parseAM3Offset() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 600 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add; in isLdstScaledRegNotPlusLsl2() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 39024 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial()
39034 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 42052 auto combineMulShlAddOrSub = [&](int Mult, int Shift, bool isAdd) { in combineMulSpecial()
42062 auto combineMulMulAddOrSub = [&](int Mul1, int Mul2, bool isAdd) { in combineMulSpecial()
|