1 /* 2 * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_MT_CIRQ_H 8 #define PLAT_MT_CIRQ_H 9 10 #include <stdint.h> 11 12 enum { 13 IRQ_MASK_HEADER = 0xF1F1F1F1, 14 IRQ_MASK_FOOTER = 0xF2F2F2F2 15 }; 16 17 struct mtk_irq_mask { 18 uint32_t header; /* for error checking */ 19 uint32_t mask0; 20 uint32_t mask1; 21 uint32_t mask2; 22 uint32_t mask3; 23 uint32_t mask4; 24 uint32_t mask5; 25 uint32_t mask6; 26 uint32_t mask7; 27 uint32_t mask8; 28 uint32_t mask9; 29 uint32_t mask10; 30 uint32_t mask11; 31 uint32_t mask12; 32 uint32_t footer; /* for error checking */ 33 }; 34 35 /* 36 * Define hardware register 37 */ 38 39 #define SYS_CIRQ_BASE U(0x10204000) 40 #define CIRQ_REG_NUM U(14) 41 #define CIRQ_IRQ_NUM U(439) 42 #define CIRQ_SPI_START U(64) 43 #define MD_WDT_IRQ_BIT_ID U(110) 44 45 #define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000)) 46 #define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080)) 47 #define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100)) 48 #define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180)) 49 #define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200)) 50 #define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280)) 51 #define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300)) 52 #define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380)) 53 #define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400)) 54 #define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480)) 55 #define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500)) 56 #define CIRQ_CON (SYS_CIRQ_BASE + U(0x600)) 57 58 /* 59 * Register placement 60 */ 61 #define CIRQ_CON_EN_BITS U(0) 62 #define CIRQ_CON_EDGE_ONLY_BITS U(1) 63 #define CIRQ_CON_FLUSH_BITS U(2) 64 #define CIRQ_CON_SW_RST_BITS U(20) 65 #define CIRQ_CON_EVENT_BITS U(31) 66 #define CIRQ_CON_BITS_MASK U(0x7) 67 68 /* 69 * Register setting 70 */ 71 #define CIRQ_CON_EN U(0x1) 72 #define CIRQ_CON_EDGE_ONLY U(0x1) 73 #define CIRQ_CON_FLUSH U(0x1) 74 #define CIRQ_SW_RESET U(0x1) 75 76 /* 77 * Define constant 78 */ 79 #define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U) 80 81 #define MT_CIRQ_POL_NEG U(0) 82 #define MT_CIRQ_POL_POS U(1) 83 84 #define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START)) 85 #define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START)) 86 87 /* GIC sensitive */ 88 #define SENS_EDGE U(0x2) 89 #define SENS_LEVEL U(0x1) 90 91 92 /* 93 * Define function prototypes. 94 */ 95 int mt_cirq_test(void); 96 void mt_cirq_dump_reg(void); 97 int mt_irq_mask_restore(struct mtk_irq_mask *mask); 98 int mt_irq_mask_all(struct mtk_irq_mask *mask); 99 void mt_cirq_clone_gic(void); 100 void mt_cirq_enable(void); 101 void mt_cirq_flush(void); 102 void mt_cirq_disable(void); 103 void mt_irq_unmask_for_sleep_ex(uint32_t irq); 104 void set_wakeup_sources(uint32_t *list, uint32_t num_of_events); 105 void mt_cirq_sw_reset(void); 106 107 struct cirq_reg { 108 uint32_t reg_num; 109 uint32_t used; 110 uint32_t mask; 111 uint32_t pol; 112 uint32_t sen; 113 uint32_t pending; 114 uint32_t the_link; 115 }; 116 117 struct cirq_events { 118 uint32_t num_reg; 119 uint32_t spi_start; 120 uint32_t num_of_events; 121 uint32_t *wakeup_events; 122 struct cirq_reg table[CIRQ_REG_NUM]; 123 uint32_t dist_base; 124 uint32_t cirq_base; 125 uint32_t used_reg_head; 126 }; 127 128 #endif /* PLAT_MT_CIRQ_H */ 129