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Searched refs:ADDR_TM_2D_TILED_THIN1 (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/amd/addrlib/src/r800/
Dciaddrlib.cpp799 ADDR_ASSERT(tileMode == ADDR_TM_2D_TILED_THIN1 || in HwlComputeFmaskInfo()
805 ADDR_ASSERT(m_tileTable[14].mode == ADDR_TM_2D_TILED_THIN1); in HwlComputeFmaskInfo()
809 INT_32 tileIndex = tileMode == ADDR_TM_2D_TILED_THIN1 ? 14 : 15; in HwlComputeFmaskInfo()
1066 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
1133 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1153 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1159 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
1393 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1412 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
1464 case ADDR_TM_2D_TILED_THIN1: in HwlSetupTileInfo()
Degbaddrlib.cpp182 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceInfo()
1130 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceMipLevelTileMode()
1253 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1263 expTileMode = ADDR_TM_2D_TILED_THIN1; in HwlDegradeThickTileMode()
1387 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceAddrFromCoord()
2252 case ADDR_TM_2D_TILED_THIN1: //fall through in DispatchComputeSurfaceCoordFromAddr()
2511 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeSurfaceCoord2DFromBankPipe()
3023 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankFromCoord()
3049 case ADDR_TM_2D_TILED_THIN1: //fall through in ComputeBankFromCoord()
3159 case ADDR_TM_2D_TILED_THIN1: // fall through in ComputeBankRotation()
Dsiaddrlib.cpp1424 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo); in HwlComputeXmaskAddrFromCoord()
3349 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOptimizeTileMode()
3380 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlOverrideTileMode()
3423 pInOut->tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSetPrtTileMode()
3460 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
3466 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
3486 tileMode = ADDR_TM_2D_TILED_THIN1; in HwlSelectTileMode()
/external/mesa3d/src/amd/addrlib/inc/
Daddrtypes.h174 ADDR_TM_2D_TILED_THIN1 = 4, ///< A set of macro tiles consist of 8x8 tiles enumerator
/external/mesa3d/src/amd/common/
Dac_surface.c551 case ADDR_TM_2D_TILED_THIN1: in gfx6_compute_level()
731 if (csio->tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_surface_settings()
881 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1; in gfx6_compute_surface()
982 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && in gfx6_compute_surface()
1004 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); in gfx6_compute_surface()
1109 if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) { in gfx6_compute_surface()
/external/mesa3d/src/amd/addrlib/src/core/
Daddrlib1.cpp2474 ADDR_TM_2D_TILED_THIN1, in HwlComputeXmaskAddrFromCoord()
3791 tileMode = ADDR_TM_2D_TILED_THIN1; in DegradeLargeThickTile()