| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 342 X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
343 X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1078 X86_INTRINSIC_DATA(sse3_addsub_pd, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1079 X86_INTRINSIC_DATA(sse3_addsub_ps, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
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| D | X86ISelLowering.h | 204 ADDSUB, enumerator
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| D | X86InstrFragmentsSIMD.td | 502 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
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| D | X86ISelLowering.cpp | 9205 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in lowerToAddSubOrFMAddSub()
29851 case X86ISD::ADDSUB: return "X86ISD::ADDSUB"; in getTargetNodeName()
35062 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in combineShuffleToAddSubOrFMAddSub()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 342 X86_INTRINSIC_DATA(avx_addsub_pd_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
343 X86_INTRINSIC_DATA(avx_addsub_ps_256, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1084 X86_INTRINSIC_DATA(sse3_addsub_pd, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
1085 X86_INTRINSIC_DATA(sse3_addsub_ps, INTR_TYPE_2OP, X86ISD::ADDSUB, 0),
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| D | X86ISelLowering.h | 208 ADDSUB, enumerator
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| D | X86InstrFragmentsSIMD.td | 511 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
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| D | X86ISelLowering.cpp | 9478 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in lowerToAddSubOrFMAddSub()
30997 NODE_NAME_CASE(ADDSUB) in getTargetNodeName()
37403 return DAG.getNode(X86ISD::ADDSUB, DL, VT, Opnd0, Opnd1); in combineShuffleToAddSubOrFMAddSub()
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | sse3-avx-addsub.ll | 6 ; Test ADDSUB ISel patterns.
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| D | fmaddsub-combine.ll | 6 ; This test checks the fusing of MUL + ADDSUB to FMADDSUB.
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| /external/llvm/test/CodeGen/X86/ |
| D | sse3-avx-addsub.ll | 6 ; Test ADDSUB ISel patterns.
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 199 ADDSUB, enumerator
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| D | X86SchedHaswell.td | 2015 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)r(Y)?",
2032 "VF(N?)M(ADD|SUB|ADDSUB|SUBADD)P(S|D)(r213|r132|r231)m(Y)?",
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| D | X86InstrFragmentsSIMD.td | 454 def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
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| D | X86ISelLowering.cpp | 6362 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1); in LowerToAddSub()
22307 case X86ISD::ADDSUB: return "X86ISD::ADDSUB"; in getTargetNodeName()
26036 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS); in combineShuffleToAddSub()
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| /external/llvm-project/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 2291 // SVE2 ADDSUB Long Unpredicated.
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 10549 // FastEmit functions for X86ISD::ADDSUB.
15145 case X86ISD::ADDSUB: return fastEmit_X86ISD_ADDSUB_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
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