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Searched refs:APSR (Results 1 – 25 of 72) sorted by relevance

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/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp1157 APSR.N = result<31>; in EmulateADDRdSPImm()
1158 APSR.Z = IsZeroBit(result); in EmulateADDRdSPImm()
1159 APSR.C = carry; in EmulateADDRdSPImm()
1160 APSR.V = overflow; in EmulateADDRdSPImm()
1218 APSR.N = result<31>; in EmulateMOVRdSP()
1219 APSR.Z = IsZeroBit(result); in EmulateMOVRdSP()
1280 APSR.N = result<31>; in EmulateMOVRdRm()
1281 APSR.Z = IsZeroBit(result); in EmulateMOVRdRm()
1371 APSR.N = result<31>; in EmulateMOVRdImm()
1372 APSR.Z = IsZeroBit(result); in EmulateMOVRdImm()
[all …]
/external/vixl/test/aarch32/
Dtest-simulator-cond-rd-rn-rm-q-t32.cc456 __ Mrs(saved_q_bit, APSR); in TestHelper()
468 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
490 __ Mrs(nzcv_bits, APSR); in TestHelper()
498 __ Mrs(q_bit, APSR); in TestHelper()
506 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-sel-t32.cc449 __ Mrs(saved_q_bit, APSR); in TestHelper()
461 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
483 __ Mrs(nzcv_bits, APSR); in TestHelper()
491 __ Mrs(q_bit, APSR); in TestHelper()
499 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-sel-a32.cc449 __ Mrs(saved_q_bit, APSR); in TestHelper()
461 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
483 __ Mrs(nzcv_bits, APSR); in TestHelper()
491 __ Mrs(q_bit, APSR); in TestHelper()
499 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-q-a32.cc456 __ Mrs(saved_q_bit, APSR); in TestHelper()
468 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
490 __ Mrs(nzcv_bits, APSR); in TestHelper()
498 __ Mrs(q_bit, APSR); in TestHelper()
506 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-ge-a32.cc472 __ Mrs(saved_q_bit, APSR); in TestHelper()
484 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
506 __ Mrs(nzcv_bits, APSR); in TestHelper()
514 __ Mrs(q_bit, APSR); in TestHelper()
522 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-ge-t32.cc472 __ Mrs(saved_q_bit, APSR); in TestHelper()
484 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
506 __ Mrs(nzcv_bits, APSR); in TestHelper()
514 __ Mrs(q_bit, APSR); in TestHelper()
522 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-operand-const-a32.cc518 __ Mrs(saved_q_bit, APSR); in TestHelper()
532 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-operand-imm16-t32.cc471 __ Mrs(saved_q_bit, APSR); in TestHelper()
485 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-utils-aarch32.cc80 __ Mrs(tmp, APSR); in Dump()
Dtest-simulator-cond-rd-operand-const-t32.cc633 __ Mrs(saved_q_bit, APSR); in TestHelper()
647 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-a32.cc555 __ Mrs(saved_q_bit, APSR); in TestHelper()
570 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-ror-amount-t32.cc620 __ Mrs(saved_q_bit, APSR); in TestHelper()
635 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-t32.cc555 __ Mrs(saved_q_bit, APSR); in TestHelper()
570 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc620 __ Mrs(saved_q_bit, APSR); in TestHelper()
635 __ Mrs(nzcv_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-t32.cc1558 __ Mrs(saved_q_bit, APSR); in TestHelper()
1570 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
1592 __ Mrs(nzcv_bits, APSR); in TestHelper()
1600 __ Mrs(q_bit, APSR); in TestHelper()
1608 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rd-rn-rm-a32.cc1560 __ Mrs(saved_q_bit, APSR); in TestHelper()
1572 __ Mrs(saved_nzcv_bits, APSR); in TestHelper()
1594 __ Mrs(nzcv_bits, APSR); in TestHelper()
1602 __ Mrs(q_bit, APSR); in TestHelper()
1610 __ Mrs(ge_bits, APSR); in TestHelper()
Dtest-simulator-cond-rdlow-rnlow-rmlow-t32.cc937 __ Mrs(saved_q_bit, APSR); in TestHelper()
953 __ Mrs(nzcv_bits, APSR); in TestHelper()
/external/llvm/test/CodeGen/ARM/
Dcopy-cpsr.ll29 ; CHECK-THUMB: msr {{APSR|apsr}}_nzcvq, [[TMP]] @ encoding: [0x8{{[0-9a-f]}},0xf3,0x00,0x88]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dcopy-cpsr.ll29 ; CHECK-THUMB: msr {{APSR|apsr}}_nzcvq, [[TMP]] @ encoding: [0x8{{[0-9a-f]}},0xf3,0x00,0x88]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMRegisterInfo.td180 // models the APSR when it's accessed by some special instructions. In such cases
183 def APSR : ARMReg<15, "apsr">;
250 // GPRs without the PC but with APSR. Some instructions allow accessing the
251 // APSR, while actually encoding PC in the register field. This is useful
261 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
262 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
/external/llvm-project/llvm/lib/Target/ARM/
DARMRegisterInfo.td180 // models the APSR when it's accessed by some special instructions. In such cases
183 def APSR : ARMReg<15, "apsr">;
250 // GPRs without the PC but with APSR. Some instructions allow accessing the
251 // APSR, while actually encoding PC in the register field. This is useful
261 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
262 def GPRwithAPSRnosp : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12), LR, APSR)> {
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td161 // models the APSR when it's accessed by some special instructions. In such cases
164 def APSR : ARMReg<1, "apsr">;
216 // GPRs without the PC but with APSR. Some instructions allow accessing the
217 // APSR, while actually encoding PC in the register field. This is useful
/external/vixl/src/aarch32/
Dinstructions-aarch32.cc210 case APSR: in GetName()
/external/swiftshader/third_party/subzero/src/
DIceInstARM32.def104 // APSR's NZCV fields). For example, EQ is 0, but corresponds to Z = 1, and NE

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