Searched refs:ARM_DRAM1_BASE (Results 1 – 13 of 13) sorted by relevance
20 #define ARM_DRAM1_BASE UL(0x80000000) macro22 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \97 #define BOOT_BASE ARM_DRAM1_BASE100 #define ARM_NS_DRAM1_BASE (ARM_DRAM1_BASE + BOOT_SIZE)271 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
24 #define ARM_DRAM1_BASE UL(0x80000000) macro26 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \34 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE258 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + U(0x8000000))
79 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \97 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \147 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE153 #define ARM_DRAM1_BASE ULL(0x80000000) macro155 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
51 #define ARM_DRAM1_BASE UL(0x80000000) macro53 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \55 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
33 #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \115 ARM_DRAM1_BASE, \
106 zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()107 flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); in dmc_ecc_setup()
43 #define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE
87 ARM_DRAM1_BASE, \
82 .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
38 #define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE
74 #define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x8000000))
183 .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
156 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; in arm_bl31_early_platform_setup()