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Searched refs:BRW_OPCODE_DO (Results 1 – 25 of 27) sorted by relevance

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/external/mesa3d/src/intel/compiler/
Dbrw_cfg.cpp116 op == BRW_OPCODE_DO || in ends_block()
125 return op == BRW_OPCODE_DO || in starts_block()
262 case BRW_OPCODE_DO: in cfg_t()
Dbrw_disasm_info.c161 if (devinfo->gen >= 6 && inst->opcode == BRW_OPCODE_DO) { in disasm_annotate()
Dbrw_fs_reg_allocate.cpp323 if (block->start()->opcode == BRW_OPCODE_DO) in count_to_loop_end()
346 case BRW_OPCODE_DO: in calculate_payload_ranges()
1015 case BRW_OPCODE_DO: in set_spill_costs()
Dbrw_cfg.h188 return op == BRW_OPCODE_DO || op == BRW_OPCODE_ENDIF; in bblock_starts_with_control_flow()
Dbrw_shader.cpp171 if (devinfo->gen >= 6 && op == BRW_OPCODE_DO) in brw_instruction_name()
915 case BRW_OPCODE_DO: in is_control_flow()
Dtest_fs_scoreboard.cpp467 bld.emit(BRW_OPCODE_DO); in TEST_F()
501 bld.emit(BRW_OPCODE_DO); in TEST_F()
534 bld.emit(BRW_OPCODE_DO); in TEST_F()
Dbrw_vec4_copy_propagation.cpp60 return (inst->opcode != BRW_OPCODE_DO && in is_dominated_by_previous_instruction()
Dbrw_vec4_reg_allocate.cpp461 case BRW_OPCODE_DO: in evaluate_spill_costs()
Dgen6_gs_visitor.cpp381 emit(BRW_OPCODE_DO); in emit_thread_end()
Dbrw_ir_performance.cpp577 case BRW_OPCODE_DO: in instruction_desc()
1553 if (inst->opcode == BRW_OPCODE_DO) in calculate_performance()
Dbrw_eu_defines.h233 BRW_OPCODE_DO, /**< Pre-Gen6 */ enumerator
Dbrw_fs_bank_conflicts.cpp641 if (inst->opcode == BRW_OPCODE_DO) { in shader_conflict_weight_matrix()
Dbrw_eu.cpp645 { BRW_OPCODE_DO, 38, "do", 0, 0, GEN_LE(GEN5) },
Dbrw_fs_scoreboard.cpp77 case BRW_OPCODE_DO: in ordered_unit()
Dbrw_eu_emit.c1825 brw_inst *insn = next_insn(p, BRW_OPCODE_DO); in brw_DO()
1918 assert(brw_inst_opcode(devinfo, do_insn) == BRW_OPCODE_DO); in brw_WHILE()
Dbrw_fs.cpp2970 if (inst->opcode == BRW_OPCODE_IF || inst->opcode == BRW_OPCODE_DO) { in opt_register_renaming()
3279 case BRW_OPCODE_DO: in eliminate_find_live_channel()
7872 case BRW_OPCODE_DO: in fixup_nomask_control_flow()
9444 bld.emit(BRW_OPCODE_DO); in brw_fs_test_dispatch_packing()
Dbrw_vec4_nir.cpp122 emit(BRW_OPCODE_DO); in nir_emit_loop()
Dbrw_vec4_generator.cpp1698 case BRW_OPCODE_DO: in generate_code()
Dbrw_vec4.cpp1482 case BRW_OPCODE_DO: in eliminate_find_live_channel()
/external/igt-gpu-tools/assembler/
Dlex.l150 "do" { yylval.integer = BRW_OPCODE_DO; return DO; }
Dbrw_eu_compact.c462 src->header.opcode == BRW_OPCODE_DO || in brw_try_compact_instruction()
Dbrw_defines.h663 BRW_OPCODE_DO = 38, enumerator
Dbrw_eu_emit.c1583 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO); in brw_DO()
1675 assert(do_insn->header.opcode == BRW_OPCODE_DO); in brw_WHILE()
Dbrw_disasm.c86 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
/external/mesa3d/src/intel/tools/
Di965_lex.l73 do { yylval.integer = BRW_OPCODE_DO; return DO; }

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