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Searched refs:BRW_VERTICAL_STRIDE_2 (Results 1 – 9 of 9) sorted by relevance

/external/igt-gpu-tools/assembler/
Dbrw_reg.h276 BRW_VERTICAL_STRIDE_2, in brw_vec2_reg()
Dbrw_defines.h822 #define BRW_VERTICAL_STRIDE_2 2 macro
/external/mesa3d/src/intel/compiler/
Dbrw_disasm.c1024 return BRW_VERTICAL_STRIDE_2; in vstride_from_align1_3src_vstride()
1051 case BRW_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2: return BRW_VERTICAL_STRIDE_2; in vstride_from_align1_3src_hstride()
1073 case BRW_VERTICAL_STRIDE_2: return BRW_WIDTH_2; in implied_width()
Dbrw_eu_defines.h1023 BRW_VERTICAL_STRIDE_2 = 2, enumerator
Dbrw_eu_validate.c949 brw_inst_src0_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 && in general_restrictions_on_region_parameters()
964 brw_inst_src1_vstride(devinfo, inst) != BRW_VERTICAL_STRIDE_2 && in general_restrictions_on_region_parameters()
Dbrw_reg.h511 BRW_VERTICAL_STRIDE_2, in brw_vec2_reg()
Dtest_eu_validate.cpp221 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2); in TEST_P()
836 { BRW_VERTICAL_STRIDE_2, devinfo.is_haswell || devinfo.gen >= 8 }, in TEST_P()
1038 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2); in TEST_P()
1089 brw_inst_set_src0_vstride(&devinfo, last_inst, BRW_VERTICAL_STRIDE_2); in TEST_P()
Dbrw_eu_emit.c326 reg.vstride == BRW_VERTICAL_STRIDE_2) { in brw_set_src0()
433 reg.vstride == BRW_VERTICAL_STRIDE_2) { in brw_set_src1()
754 case BRW_VERTICAL_STRIDE_2: in to_3src_align1_vstride()
Dbrw_fs_generator.cpp1333 vstride = BRW_VERTICAL_STRIDE_2; in generate_ddx()