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Searched refs:BeginBlock (Results 1 – 13 of 13) sorted by relevance

/external/tensorflow/tensorflow/java/src/gen/cc/
Dsource_writer.cc112 SourceWriter& SourceWriter::BeginBlock(const string& expression) { in BeginBlock() function in tensorflow::java::SourceWriter
158 return Append(")").BeginBlock(); in BeginMethod()
220 return BeginBlock(); in BeginInnerType()
Dsource_writer_test.cc224 .BeginBlock() in TEST()
227 .BeginBlock() in TEST()
272 .BeginBlock() in TEST()
517 .BeginBlock() in TEST()
Dop_generator.cc124 .BeginBlock("for (int i = 0; i < " + array_name + ".length; ++i)") in WriteSetAttrDirective()
254 writer->BeginBlock("if (options != null)") in RenderFactoryMethods()
255 .BeginBlock("for (Options opts : options)"); in RenderFactoryMethods()
257 writer->BeginBlock("if (opts." + attribute.var().name() + " != null)"); in RenderFactoryMethods()
Dsource_writer.h96 SourceWriter& BeginBlock(const string& expression = "");
/external/pdfium/fxjs/
Dcjs_runtime.h48 void BeginBlock() { m_bBlocking = true; } in BeginBlock() function
Dcjs_document.cpp342 pRuntime->BeginBlock(); in mailDoc()
393 pRuntime->BeginBlock(); in mailForm()
599 pRuntime->BeginBlock(); in submitForm()
620 pRuntime->BeginBlock(); in submitForm()
1386 pRuntime->BeginBlock(); in gotoNamedDest()
Dcjs_app.cpp252 pRuntime->BeginBlock(); in alert()
455 pRuntime->BeginBlock(); in mailMsg()
/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h144 void schedule(MachineBasicBlock::iterator BeginBlock,
203 void initRegPressure(MachineBasicBlock::iterator BeginBlock,
DSIMachineScheduler.cpp305 void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock, in initRegPressure() argument
360 isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(), in initRegPressure()
378 void SIScheduleBlock::schedule(MachineBasicBlock::iterator BeginBlock, in schedule() argument
384 initRegPressure(BeginBlock, EndBlock); in schedule()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h152 void schedule(MachineBasicBlock::iterator BeginBlock,
209 void initRegPressure(MachineBasicBlock::iterator BeginBlock,
DSIMachineScheduler.cpp325 void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock, in initRegPressure() argument
380 isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(), in initRegPressure()
398 void SIScheduleBlock::schedule(MachineBasicBlock::iterator BeginBlock, in schedule() argument
404 initRegPressure(BeginBlock, EndBlock); in schedule()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h152 void schedule(MachineBasicBlock::iterator BeginBlock,
209 void initRegPressure(MachineBasicBlock::iterator BeginBlock,
DSIMachineScheduler.cpp325 void SIScheduleBlock::initRegPressure(MachineBasicBlock::iterator BeginBlock, in initRegPressure() argument
380 isDefBetween(Reg, LIS->getInstructionIndex(*BeginBlock).getRegSlot(), in initRegPressure()
398 void SIScheduleBlock::schedule(MachineBasicBlock::iterator BeginBlock, in schedule() argument
404 initRegPressure(BeginBlock, EndBlock); in schedule()