| /external/llvm-project/lldb/source/Plugins/Instruction/ARM/ |
| D | EmulateInstructionARM.cpp | 615 ITCounter = CountITSize(Bits32(bits7_0, 3, 0)); in InitIT()
620 unsigned short FirstCond = Bits32(bits7_0, 7, 4); in InitIT()
639 unsigned short NewITState4_0 = Bits32(ITState, 4, 0) << 1; in ITAdvance()
653 return Bits32(ITState, 7, 4); in GetCond()
933 registers = Bits32(opcode, 7, 0); in EmulatePUSH()
943 registers = Bits32(opcode, 15, 0) & ~0xa000; in EmulatePUSH()
949 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
956 registers = Bits32(opcode, 15, 0); in EmulatePUSH()
962 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
1048 registers = Bits32(opcode, 7, 0); in EmulatePOP()
[all …]
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| /external/llvm-project/lldb/source/Plugins/Instruction/PPC64/ |
| D | EmulateInstructionPPC64.cpp | 214 uint32_t rt = Bits32(opcode, 25, 21); in EmulateMFSPR()
215 uint32_t spr = Bits32(opcode, 20, 11); in EmulateMFSPR()
239 uint32_t rt = Bits32(opcode, 25, 21); in EmulateLD()
240 uint32_t ra = Bits32(opcode, 20, 16); in EmulateLD()
241 uint32_t ds = Bits32(opcode, 15, 2); in EmulateLD()
268 uint32_t rs = Bits32(opcode, 25, 21); in EmulateSTD()
269 uint32_t ra = Bits32(opcode, 20, 16); in EmulateSTD()
270 uint32_t ds = Bits32(opcode, 15, 2); in EmulateSTD()
271 uint32_t u = Bits32(opcode, 1, 0); in EmulateSTD()
335 uint32_t rs = Bits32(opcode, 25, 21); in EmulateOR()
[all …]
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| /external/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| D | EmulateInstructionARM64.cpp | 627 const uint32_t shift = Bits32(opcode, 23, 22); in EmulateADDSUBImm()
628 const uint32_t imm12 = Bits32(opcode, 21, 10); in EmulateADDSUBImm()
629 const uint32_t Rn = Bits32(opcode, 9, 5); in EmulateADDSUBImm()
630 const uint32_t Rd = Bits32(opcode, 4, 0); in EmulateADDSUBImm()
704 uint32_t opc = Bits32(opcode, 31, 30); in EmulateLDPSTP()
707 uint32_t imm7 = Bits32(opcode, 21, 15); in EmulateLDPSTP()
708 uint32_t Rt2 = Bits32(opcode, 14, 10); in EmulateLDPSTP()
709 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP()
710 uint32_t Rt = Bits32(opcode, 4, 0); in EmulateLDPSTP()
927 uint32_t size = Bits32(opcode, 31, 30); in EmulateLDRSTRImm()
[all …]
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| /external/llvm-project/lldb/source/Plugins/Architecture/Arm/ |
| D | ArchitectureArm.cpp | 106 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28); in OverrideStopInfo()
118 const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25); in OverrideStopInfo()
120 const uint32_t condition = Bits32(ITSTATE, 7, 4); in OverrideStopInfo()
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| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | ARMUtils.h | 55 return DecodeImmShift(Bits32(opcode, 5, 4), in DecodeImmShiftThumb()
56 Bits32(opcode, 14, 12) << 2 | Bits32(opcode, 7, 6), in DecodeImmShiftThumb()
64 return DecodeImmShift(Bits32(opcode, 6, 5), Bits32(opcode, 11, 7), shift_t); in DecodeImmShiftARM()
198 return Bit32(carry_in, 0) << 31 | Bits32(value, 31, 1); in RRX_C()
266 return Bits32(val, msbit, lsbit); in bits()
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| D | InstructionUtils.h | 29 static inline uint32_t Bits32(const uint32_t bits, const uint32_t msbit, in Bits32() function
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| D | RegisterContextDarwin_arm.cpp | 1509 g_num_supported_hw_breakpoints = Bits32(register_DBGDIDR, 27, 24); in NumSupportedHardwareBreakpoints()
1638 g_num_supported_hw_watchpoints = Bits32(register_DBGDIDR, 31, 28) + 1; in NumSupportedHardwareWatchpoints()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 1873 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ() local
1874 SDValue Add = DAG.getNode(ISD::ADD, SL, MVT::i32, CtlzLo, Bits32); in LowerCTLZ()
1892 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ() local
1897 SrcIsZero, Bits32, NewCtlz); in LowerCTLZ()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2359 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ() local
2362 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32); in LowerCTLZ_CTTZ()
2366 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32); in LowerCTLZ_CTTZ()
2385 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ() local
2390 SrcIsZero, Bits32, NewOpr); in LowerCTLZ_CTTZ()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2357 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32); in LowerCTLZ_CTTZ() local
2360 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32); in LowerCTLZ_CTTZ()
2364 Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32); in LowerCTLZ_CTTZ()
2383 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32); in LowerCTLZ_CTTZ() local
2388 SrcIsZero, Bits32, NewOpr); in LowerCTLZ_CTTZ()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7123 unsigned Bits32 = 0; in LowerBUILD_VECTOR_i1() local
7130 Bits32 |= BoolMask << (i * BitsPerBool); in LowerBUILD_VECTOR_i1()
7135 DAG.getConstant(Bits32, dl, MVT::i32)); in LowerBUILD_VECTOR_i1()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 7422 unsigned Bits32 = 0; in LowerBUILD_VECTOR_i1() local
7429 Bits32 |= BoolMask << (i * BitsPerBool); in LowerBUILD_VECTOR_i1()
7434 DAG.getConstant(Bits32, dl, MVT::i32)); in LowerBUILD_VECTOR_i1()
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