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/external/llvm-project/clang/test/CodeGenCXX/
Dlto-visibility-inference.cpp54 struct C10 { struct
69 std::C7::C8 *c8, stdext::C9 *c9, other::C10 *c10) { in f()
/external/clang/test/CodeGenCXX/
Dlto-visibility-inference.cpp54 struct C10 { struct
69 std::C7::C8 *c8, stdext::C9 *c9, other::C10 *c10) { in f()
/external/llvm-project/mlir/test/Dialect/Linalg/
Dtile-indexed-generic.mlir25 // TILE-10n25: %[[C10:.*]] = constant 10 : index
26 // TILE-10n25: scf.for %[[J:.*]] = {{.*}} step %[[C10]]
73 // TILE-10n25-DAG: %[[C10:.*]] = constant 10 : index
74 // TILE-10n25: scf.for %[[K:.*]] = {{.*}} step %[[C10]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fptrunc.mir117 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
118 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
129 ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[C10]]
197 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
198 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
209 ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD]](s32), [[C10]]
250 ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD2]]
259 ; CHECK: [[ICMP11:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[ADD2]](s32), [[C10]]
324 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
325 ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[ADD]]
[all …]
Dlegalize-merge-values.mir275 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
276 ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
297 ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[C10]](s32)
340 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
341 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
364 ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND6]], [[C10]](s32)
417 ; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
418 ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C10]](s32)
489 ; CHECK: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
490 ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[C10]], [[C4]]
[all …]
Dlegalize-fptoui.mir195 ; SI: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
196 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
255 ; SI: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
256 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]]
314 ; SI: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FEFFFFFFFFFFFFF
315 ; SI: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
338 ; SI: [[FMINNUM_IEEE1:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT3]], [[C10]]
440 ; SI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
441 ; SI: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[SELECT3]], [[C10]]
504 ; VI: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 -9223372036854775808
[all …]
Dregbankselect-extract-vector-elt.mir79 ; WAVE64: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
80 ; WAVE64: [[ICMP10:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C10]]
131 ; WAVE32: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
132 ; WAVE32: [[ICMP10:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C10]]
225 ; WAVE64: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
226 ; WAVE64: [[ICMP10:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C10]]
277 ; WAVE32: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 11
278 ; WAVE32: [[ICMP10:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C10]]
588 ; WAVE64: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10
589 ; WAVE64: [[ICMP9:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[ADD]](s32), [[C10]]
[all …]
/external/llvm-project/mlir/test/Transforms/
Dparallel-loop-collapsing.mlir32 // CHECK: [[C10:%.*]] = constant 10 : index
41 // CHECK: [[V2:%.*]] = muli [[V0]], [[C10]] : index
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-callingconv-ios.ll32 ; CHECK: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
33 ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C10]](s64)
64 ; CHECK: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
86 ; CHECK: G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store 1 into stack + 4)
/external/cldr/tools/java/org/unicode/cldr/draft/keyboard/test/
DKeyboardTest.java45 CharacterMap characterMap6 = CharacterMap.of(IsoLayoutPosition.C10, "\u0302"); in createKeyboard()
89 CharacterMap characterMap6 = CharacterMap.of(IsoLayoutPosition.C10, "\u0302"); in testKeyMaps()
123 CharacterMap characterMap6 = CharacterMap.of(IsoLayoutPosition.C10, "\u0302"); in testEqualsTrue()
/external/cldr/tools/java/org/unicode/cldr/draft/keyboard/windows/
Dwindows-keycodes.csv36 39,C10
/external/cldr/tools/java/org/unicode/cldr/draft/keyboard/osx/
Dosx-keycodes.csv38 41,C10
/external/llvm-project/clang/test/Coverage/
Dast-print-temp-class.cpp26 template<typename T = int> class C10 {}; class
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dand-or-icmps.ll215 ; CHECK-NEXT: [[C10:%.*]] = icmp ugt i16 [[L7]], [[B11]]
219 ; CHECK-NEXT: [[B15:%.*]] = xor i1 [[C7]], [[C10]]
221 ; CHECK-NEXT: [[TMP2:%.*]] = and i1 [[C10]], [[C5]]
223 ; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[C10]], true
244 %C10 = icmp ugt i16 %L, %B11
246 %B1 = mul i1 %C10, true
251 %B15 = add i1 %C7, %C10
258 %C18 = icmp ule i1 %C10, %C7
/external/cldr/tools/java/org/unicode/cldr/draft/keyboard/
DIsoLayoutPosition.java39 …"L"), C10('C', 10, ";"), C11('C', 11, "'"), C12('C', 12, "(key to right of ')"), // Additional key… enumConstant
/external/autotest/client/site_tests/power_SuspendToIdle/
Dcontrol24 5. CPU package C10 state residency counter is increased.
Dcontrol.force23 5. CPU package C10 state residency counter is increased.
/external/llvm-project/clang/test/Parser/
Dcxx2a-concept-declaration.cpp67 template<typename T> concept A::C10 = false;
/external/llvm-project/llvm/test/Analysis/ScalarEvolution/
Dexact-exit-count-more-precise.ll63 %C10 = icmp slt i1 undef, undef
64 br i1 %C10, label %BB, label %exit
/external/llvm-project/llvm/test/CodeGen/X86/
Dvec_extract.ll119 %C10 = icmp ule i1 false, false
121 %B = sdiv i1 %C10, %C3
/external/llvm-project/clang/test/SemaCXX/
Dms-uuid.cpp95 uuid("000000A0-0000-0000-C000-000000000049")] class C10;
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Daix-cc-ext-vec-abi.ll72 ; ASM32-DAG: lwz [[REG11:[0-9]+]], L..C10(2)
106 ; ASM64-DAG: ld [[REG11:[0-9]+]], L..C10(2)
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td223 def C10 : Ri< 10, "C10">;
307 def C10_C11 : Rdi<10, "C10", [C10, C11]>;
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td224 def C10 : Ri< 10, "C10">;
308 def C10_C11 : Rdi<10, "C10", [C10, C11]>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td223 def C10 : Ri< 10, "C10">;
307 def C10_C11 : Rdi<10, "C10", [C10, C11]>;

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