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Searched refs:COND0 (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeon/
Dradeon_vcn_dec_jpeg.c71 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); in send_cmd_bitstream()
74 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); in send_cmd_bitstream()
75 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); in send_cmd_bitstream()
76 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); in send_cmd_bitstream()
77 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); in send_cmd_bitstream()
78 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); in send_cmd_bitstream()
81 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); in send_cmd_bitstream()
84 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); in send_cmd_bitstream()
85 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); in send_cmd_bitstream()
86 set_reg_jpeg(dec, SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); in send_cmd_bitstream()
[all …]
Dradeon_vcn_dec.h204 #define COND0 0 macro
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dxor-of-icmps-with-extra-uses.ll26 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[X:%.*]], 32768
27 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 -32768, i32 [[Y:%.*]]
61 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[X:%.*]], 32768
62 ; CHECK-NEXT: br i1 [[COND0]], label [[BB1:%.*]], label [[BB0:%.*]]
92 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[X:%.*]], 32768
93 ; CHECK-NEXT: store i1 [[COND0]], i1* [[NOT_COND:%.*]], align 1
110 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[X:%.*]], 32768
111 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND0]], i32 [[Y:%.*]], i32 32767
112 ; CHECK-NEXT: store i1 [[COND0]], i1* [[NOT_COND:%.*]], align 1
131 ; CHECK-NEXT: [[COND0:%.*]] = icmp sgt i32 [[X:%.*]], 32767
[all …]
/external/llvm-project/llvm/test/Transforms/JumpThreading/
Dthreadable-edge-cast.ll11 ; CHECK-NEXT: br i1 [[COND0:%.*]], label [[T1:%.*]], label [[F1:%.*]]
51 ; CHECK-NEXT: br i1 [[COND0:%.*]], label [[T1:%.*]], label [[F1:%.*]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-icmp.mir20 # GCN-NEXT: [[COND0:%[0-9]+]]:sreg_32 = COPY $scc
23 # GCN: $scc = COPY [[COND0]]
133 # GCN: [[COND0:%[0-9]+]]:[[VCCRC]] = V_CMP_NE_U32_e64 [[VGPR2]], [[VGPR3]]
135 # GCN: V_CNDMASK_B32_e64 0, [[VGPR9]], 0, [[VGPR8]], [[COND0]]
/external/llvm-project/llvm/test/Transforms/EarlyCSE/
Dguards.ll65 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[VAL:%.*]], 40
66 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND0]]) [ "deopt"() ]
84 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[VAL:%.*]], 40
85 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND0]]) [ "deopt"() ]
104 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[VAL:%.*]], 40
105 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND0]]) [ "deopt"() ]
145 ; CHECK-NEXT: [[COND0:%.*]] = icmp slt i32 [[VAL:%.*]], 40
146 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND0]]) [ "deopt"() ]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Duniform-cfg.ll251 ; GCN: s_load_dwordx2 s{{\[}}[[COND0:[0-9]+]]:[[COND1:[0-9]+]]{{\]}}
252 ; GCN: s_cmp_lt_i32 s[[COND0]], 1