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Searched refs:CSSELR (Results 1 – 7 of 7) sorted by relevance

/external/arm-trusted-firmware/lib/aarch32/
Dcache_helpers.S103 stcopr r1, CSSELR // select current cache level in csselr
133 stcopr r6, CSSELR //select cache level 0 in csselr
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/
Dcore_cm7.h525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2130 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_EnableDCache()
2168 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_DisableDCache()
2205 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_InvalidateDCache()
2240 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanDCache()
2275 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/
Dcore_cm7.h525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2130 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_EnableDCache()
2168 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_DisableDCache()
2205 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_InvalidateDCache()
2240 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanDCache()
2275 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
/external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/
Ddevice1.ini53 CSSELR=0x00000002 key
/external/arm-trusted-firmware/include/arch/aarch32/
Darch_helpers.h249 DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR) in DEFINE_SYSREG_RW_FUNCS()
Darch.h544 #define CSSELR p15, 2, c0, c0, 0 macro
/external/OpenCSD/decoder/tests/snapshots/trace_cov_a15/
Ddevice1.ini53 CSSELR=0x00000002 key