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Searched refs:CfgVector (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/subzero/src/
DIceRegAlloc.h52 using OrderedRanges = CfgVector<Variable *>;
53 using UnorderedRanges = CfgVector<Variable *>;
76 const CfgVector<InstNumberT> &LRBegin,
77 const CfgVector<InstNumberT> &LREnd) const;
123 CfgVector<InstNumberT> Kills;
134 CfgVector<Variable *> Vars;
DIceLoopAnalyzer.cpp38 CfgVector<CfgUnorderedSet<SizeT>> getLoopBodies() { return Loops; } in getLoopBodies()
95 using LoopNodeList = CfgVector<LoopNode>;
96 using LoopNodePtrList = CfgVector<LoopNode *>;
118 CfgVector<CfgUnorderedSet<SizeT>> Loops;
257 CfgVector<Loop> ComputeLoopInfo(Cfg *Func) { in ComputeLoopInfo()
260 CfgVector<Loop> Loops; in ComputeLoopInfo()
DIceCfg.h291 void sortAndCombineAllocas(CfgVector<InstAlloca *> &Allocas,
295 CfgVector<Inst *>
326 CfgVector<InstJumpTable *> JumpTables;
332 CfgVector<Loop> LoopInfo;
DIceCfg.cpp374 CfgVector<PlacedList::iterator> PlaceIndex(Nodes.size(), NoPlace); in reorderNodes()
598 CfgVector<Inst *>
610 CfgVector<std::reference_wrapper<Inst>> Insts(Node->getInsts().begin(), in findLoopInvariantInstructions()
653 CfgVector<Inst *> InstVector(InvariantInsts.begin(), InvariantInsts.end()); in findLoopInvariantInstructions()
684 CfgUnorderedMap<SizeT, CfgVector<CfgNode *>> Splits; in shortCircuitJumps()
752 CfgUnorderedMap<Constant *, CfgVector<InstList::iterator>> FloatUses; in floatConstantCSE()
813 void Cfg::sortAndCombineAllocas(CfgVector<InstAlloca *> &Allocas, in sortAndCombineAllocas()
832 CfgVector<int32_t> Offsets; in sortAndCombineAllocas()
966 CfgVector<InstAlloca *> FixedAllocas; in processAllocas()
969 CfgVector<InstAlloca *> AlignedAllocas; in processAllocas()
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DIceDefs.h143 template <typename T> using CfgVector = std::vector<T, CfgLocalAllocator<T>>; variable
146 using OperandList = CfgVector<Operand *>;
147 using VarList = CfgVector<Variable *>;
148 using NodeList = CfgVector<CfgNode *>;
DIceLoopAnalyzer.h29 CfgVector<Loop> ComputeLoopInfo(Cfg *Func);
DIceVariableSplitting.cpp150 CfgVector<VarInfo> Map;
433 CfgVector<Variable *> LinkedToFixups;
516 CfgVector<Variable *> LinkedToFixups; in splitBlockLocalVariables()
DIceTargetLoweringMIPS32.h745 inline void discardNextGPRAndItsAliases(CfgVector<RegNumT> *Regs);
746 inline void alignGPR(CfgVector<RegNumT> *Regs);
747 void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs);
749 CfgVector<RegNumT> GPRArgs;
750 CfgVector<RegNumT> I64Args;
752 void discardUnavailableVFPRegsAndTheirAliases(CfgVector<RegNumT> *Regs);
754 CfgVector<RegNumT> FP32Args;
755 CfgVector<RegNumT> FP64Args;
DIceSwitchLowering.h27 using CaseClusterArray = CfgVector<CaseCluster>;
DIceTargetLoweringARM32.h1271 void discardUnavailableGPRsAndTheirAliases(CfgVector<RegNumT> *Regs);
1273 CfgVector<RegNumT> GPRArgs;
1274 CfgVector<RegNumT> I64Args;
1276 void discardUnavailableVFPRegs(CfgVector<RegNumT> *Regs);
1278 CfgVector<RegNumT> FP32Args;
1279 CfgVector<RegNumT> FP64Args;
1280 CfgVector<RegNumT> Vec128Args;
DIceTargetLowering.cpp529 CfgVector<Inst *> getInstructionsInRange(CfgNode *Node, InstNumberT Start, in getInstructionsInRange()
531 CfgVector<Inst *> Result; in getInstructionsInRange()
797 CfgVector<size_t> LocalsSize(Func->getNumNodes()); in getVarStackSlotParams()
902 CfgVector<size_t> LocalsSize(Func->getNumNodes()); in assignVarStackSlots()
DIceRegAlloc.cpp162 const CfgVector<InstNumberT> &LRBegin, in livenessValidateIntervals()
163 const CfgVector<InstNumberT> &LREnd) const { in livenessValidateIntervals()
216 CfgVector<InstNumberT> LRBegin(Vars.size(), Inst::NumberSentinel); in initForInfOnly()
217 CfgVector<InstNumberT> LREnd(Vars.size(), Inst::NumberSentinel); in initForInfOnly()
DIceOperand.h608 using RangeType = CfgVector<RangeElementType>;
612 explicit LiveRange(const CfgVector<InstNumberT> &Kills) { in LiveRange()
1023 using InstDefList = CfgVector<const Inst *>;
1130 CfgVector<VariableTracking> Metadata;
DIceCfgNode.cpp953 bool IsLiveIn, CfgVector<SizeT> &LiveRegCount) { in emitRegisterUsage()
968 CfgVector<Variable *> LiveRegs; in emitRegisterUsage()
1002 CfgVector<SizeT> &LiveRegCount) { in emitLiveRangesEnded()
1070 CfgVector<SizeT> LiveRegCount(Func->getTarget()->getNumRegisters()); in emit()
DIceInst.h255 CfgVector<Operand *> Srcs;
702 CfgVector<CfgNode *> Labels;
DIceTargetLoweringMIPS32.cpp122 CfgVector<size_t> LocalsSize(Func->getNumNodes()); in assignVarStackSlots()
1187 CfgVector<RegNumT> *Source; in argInGPR()
1249 CfgVector<RegNumT> *Regs) { in discardNextGPRAndItsAliases()
1254 inline void TargetMIPS32::CallingConv::alignGPR(CfgVector<RegNumT> *Regs) { in alignGPR()
1265 CfgVector<RegNumT> *Regs) { in discardUnavailableGPRsAndTheirAliases()
1272 CfgVector<RegNumT> *Source; in argInVFP()
1319 CfgVector<RegNumT> *Regs) { in discardUnavailableVFPRegsAndTheirAliases()
3340 CfgVector<Variable *> RegArgs; in lowerCall()
DIceTargetLoweringX86BaseImpl.h2683 CfgVector<std::pair<const Type, Operand *>> GprArgs;
2684 CfgVector<SizeT> GprArgIndices;
4803 CfgVector<InstAssign *> PhiAssigns;
7587 CfgVector<Type> ArgTypes;
7645 const CfgVector<Type> &ArgTypes, Type ReturnType) {
7693 CfgVector<Type> ArgTypes;
DIceTargetLoweringARM32.cpp1258 CfgVector<RegNumT> *Source; in argInGPR()
1292 CfgVector<RegNumT> *Regs) { in discardUnavailableGPRsAndTheirAliases()
1300 CfgVector<RegNumT> *Source; in argInVFP()
1330 CfgVector<RegNumT> *Regs) { in discardUnavailableVFPRegs()
3824 CfgVector<Variable *> RegArgs; in lowerCall()
DIceTargetLoweringX86Base.h290 uint32_t getCallStackArgumentsSizeBytes(const CfgVector<Type> &ArgTypes,