| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | callbr-asm-bb-exports.ll | 11 ; CHECK-NEXT: t12: ch = CopyToReg t0, Register:i32 %0, t10
14 ; CHECK-NEXT: t15: ch = CopyToReg t0, Register:i32 %1, t13
18 ; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 270 SDValue CopyToReg = in SelectInlineAsmMemoryOperand() local
274 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
299 SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op); in SelectInlineAsmMemoryOperand() local
301 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRISelDAGToDAG.cpp | 267 SDValue CopyToReg = in SelectInlineAsmMemoryOperand() local
271 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
296 SDValue CopyToReg = CurDAG->getCopyToReg(Op, dl, VReg, Op); in SelectInlineAsmMemoryOperand() local
298 CurDAG->getCopyFromReg(CopyToReg, dl, VReg, TL.getPointerTy(DL)); in SelectInlineAsmMemoryOperand()
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | copy-to-reg.ll | 4 ; Test that CopyToReg instructions don't have non-register operands prior
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | copy-to-reg.ll | 4 ; Test that CopyToReg instructions don't have non-register operands prior
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 85 case ISD::CopyToReg: break; in numberRCValPredInSU()
122 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
445 case ISD::CopyToReg: in SUSchedulingCost()
|
| D | InstrEmitter.cpp | 113 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
228 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
484 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
950 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
994 case ISD::CopyToReg: { in EmitSpecialNode()
|
| D | ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
426 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
656 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
|
| D | ScheduleDAGRRList.cpp | 710 case ISD::CopyToReg: in EmitNode()
2033 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2249 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2335 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2383 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2712 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2954 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 89 case ISD::CopyToReg: break; in numberRCValPredInSU()
126 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
449 case ISD::CopyToReg: in SUSchedulingCost()
|
| D | InstrEmitter.cpp | 116 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
236 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
483 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
1017 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
1077 case ISD::CopyToReg: { in EmitSpecialNode()
|
| D | ScheduleDAGSDNodes.cpp | 115 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
429 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
660 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
|
| D | ScheduleDAGRRList.cpp | 710 case ISD::CopyToReg: in EmitNode()
2036 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2252 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2338 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2386 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2715 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2957 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 114 if (User->getOpcode() == ISD::CopyToReg && in EmitCopyFromReg()
197 if (User->getOpcode() == ISD::CopyToReg && in getDstOfOnlyCopyToRegUse()
246 if (User->getOpcode() == ISD::CopyToReg && in CreateVirtualRegisters()
479 if (User->getOpcode() == ISD::CopyToReg && in EmitSubregNode()
853 } else if (F->getOpcode() == ISD::CopyToReg) { in EmitMachineNode()
897 case ISD::CopyToReg: { in EmitSpecialNode()
|
| D | ResourcePriorityQueue.cpp | 89 case ISD::CopyToReg: break; in numberRCValPredInSU()
126 case ISD::CopyToReg: NumberDeps++; break; in numberRCValSuccInSU()
457 case ISD::CopyToReg: in SUSchedulingCost()
|
| D | ScheduleDAGSDNodes.cpp | 114 if (Op != 2 || User->getOpcode() != ISD::CopyToReg) in CheckForPhysRegDependency()
409 if (SUNode->getOpcode() != ISD::CopyToReg) in BuildSchedUnits()
639 if (Latency > 1 && Use->getOpcode() == ISD::CopyToReg && in computeOperandLatency()
|
| D | ScheduleDAGRRList.cpp | 681 case ISD::CopyToReg: in EmitNode()
1890 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in getNodePriority()
2107 if (N->getOpcode() != ISD::CopyToReg) in unscheduledNode()
2193 Succ.getSUnit()->getNode()->getOpcode() == ISD::CopyToReg) in closestSucc()
2241 if (SuccSU->getNode() && SuccSU->getNode()->getOpcode() == ISD::CopyToReg) { in hasOnlyLiveOutUses()
2570 if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg) in canEnableCoalescing()
2811 if (N->getOpcode() == ISD::CopyToReg && in PrescheduleNodesWithMultipleUses()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 165 CopyToReg, enumerator
|
| D | SelectionDAG.h | 584 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
595 return getNode(ISD::CopyToReg, dl, VTs,
604 return getNode(ISD::CopyToReg, dl, VTs,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 171 CopyToReg, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 196 CopyToReg, enumerator
|
| /external/llvm/test/CodeGen/WebAssembly/ |
| D | userstack.ll | 192 ; The use of the alloca in a phi causes a CopyToReg DAG node to be generated,
193 ; which has to have special handling because CopyToReg can't have a FI operand
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 116 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
554 case ISD::CopyToReg: in LowerOperation()
|
| /external/llvm-project/llvm/test/CodeGen/WebAssembly/ |
| D | userstack.ll | 269 ; The use of the alloca in a phi causes a CopyToReg DAG node to be generated,
270 ; which has to have special handling because CopyToReg can't have a FI operand
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1420 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg); in LowerBRCOND() local
1421 if (!CopyToReg) in LowerBRCOND()
1426 CopyToReg->getOperand(1), in LowerBRCOND()
1430 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0)); in LowerBRCOND()
|