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Searched refs:DEBUG_PIPE_CONTROL (Results 1 – 4 of 4) sorted by relevance

/external/mesa3d/src/intel/dev/
Dgen_debug.h92 #define DEBUG_PIPE_CONTROL (1ull << 45) macro
Dgen_debug.c94 { "pc", DEBUG_PIPE_CONTROL },
/external/mesa3d/src/gallium/drivers/iris/
Diris_batch.c687 if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT | DEBUG_PIPE_CONTROL)) { in _iris_batch_flush()
Diris_state.c7520 if (INTEL_DEBUG & DEBUG_PIPE_CONTROL) { in iris_emit_raw_pipe_control()