| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 180 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(24), DR(dst)); in emit_single_op()
195 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(16), DR(dst)); in emit_single_op()
483 …FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(OTHER_FLAG) | SH_IMM(31), OTHER_F… in emit_single_op()
507 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV); in emit_single_op()
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| D | sljitNativeMIPS_common.c | 193 #define DSRA32 (HI(0) | LO(63)) macro
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 76 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 83 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 83 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 161 def DSRA32 : StdMMR6Rel, shift_rotate_imm<"dsra32", uimm5, GPR64Opnd,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 186 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 186 def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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| D | MipsScheduleGeneric.td | 127 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL,
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 1085 {DBGFIELD("DSRA32") 1, false, false, 1, 2, 1, 1, 0, 0}, // #825
2769 {DBGFIELD("DSRA32") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #825
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| D | MipsGenMCCodeEmitter.inc | 1412 UINT64_C(63), // DSRA32
5336 case Mips::DSRA32:
10874 CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1399
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| D | MipsGenAsmWriter.inc | 2640 268452069U, // DSRA32
5394 4U, // DSRA32
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| D | MipsGenAsmMatcher.inc | 6498 …{ 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AM…
6499 …{ 3889 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AM…
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| D | MipsGenInstrInfo.inc | 1414 DSRA32 = 1399,
3605 DSRA32 = 825,
6260 …odeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1399 = DSRA32
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| D | MipsGenDisassemblerTables.inc | 6955 /* 495 */ MCD::OPC_Decode, 247, 10, 240, 2, // Opcode: DSRA32
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 658 134234303U, // DSRA32
2447 1U, // DSRA32
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| D | MipsGenDisassemblerTables.inc | 4360 /* 370 */ MCD_OPC_Decode, 129, 5, 254, 1, // Opcode: DSRA32
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5194 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, in expandMulO()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5084 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32, in expandMulO()
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