| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | fpbr.ll | 1 … < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
2 … < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
4 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC
5 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC
12 ; 32-FCC: c.eq.s $f12, $f14
13 ; 32-FCC: bc1f $BB0_2
14 ; 64-FCC: c.eq.s $f12, $f13
15 ; 64-FCC: bc1f .LBB0_2
48 ; 32-FCC: c.olt.s $f12, $f14
49 ; 32-FCC: bc1f $BB1_2
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fpbr.ll | 1 …s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
2 …s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
4 ; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
5 ; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
12 ; 32-FCC: c.eq.s $f12, $f14
13 ; 64-FCC: c.eq.s $f12, $f13
14 ; FCC: bc1f $BB0_2
47 ; 32-FCC: c.olt.s $f12, $f14
48 ; 64-FCC: c.olt.s $f12, $f13
49 ; FCC: bc1f $BB1_2
[all …]
|
| D | analyzebranch.ll | 1 ; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,FCC
2 ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,FCC
4 ; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,FCC
5 ; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,FCC
6 ; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,FCC
13 ; FCC: bc1f $BB
14 ; FCC: nop
46 ; FCC: bc1f $BB
47 ; FCC: nop
|
| /external/clang/test/CXX/concepts-ts/dcl.dcl/dcl.spec/dcl.spec.concept/ |
| D | p2.cpp | 13 template<typename T> concept constexpr bool FCC() { return true; } // expected-error {{function con… in FCC() function
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.h | 80 using FCC = enum { FCC0 = 0, FCC1, FCC2, FCC3, FCC4, FCC5, FCC6, FCC7 };
81 static OperandMIPS32FCC *create(Cfg *Func, OperandMIPS32FCC::FCC FCC) { in create() argument
82 return new (Func->allocate<OperandMIPS32FCC>()) OperandMIPS32FCC(FCC); in create()
85 OperandMIPS32FCC::FCC getFCC() const { return FpCondCode; } in getFCC()
106 OperandMIPS32FCC(OperandMIPS32FCC::FCC CC) in OperandMIPS32FCC()
109 const OperandMIPS32FCC::FCC FpCondCode;
1151 Variable *Src, Operand *FCC) { in create() argument
1153 InstMIPS32MovConditional(Func, Dest, Src, FCC); in create()
1188 Operand *FCC) in InstMIPS32MovConditional() argument
1191 addSource(FCC); in InstMIPS32MovConditional()
|
| D | IceTargetLoweringMIPS32.h | 414 void _movf(Variable *Dest, Variable *Src0, Operand *FCC) { in _movf() argument
415 Context.insert<InstMIPS32Movf>(Dest, Src0, FCC)->setDestRedefined(); in _movf()
430 void _movt(Variable *Dest, Variable *Src0, Operand *FCC) { in _movt() argument
431 Context.insert<InstMIPS32Movt>(Dest, Src0, FCC)->setDestRedefined(); in _movt()
|
| D | IceAssemblerMIPS32.cpp | 842 OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0; in movf()
877 OperandMIPS32FCC::FCC Cc = OperandMIPS32FCC::FCC0; in movt()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 202 def FCC#I : MipsReg<#I, "fcc"#I>;
396 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
621 def FCCRegsOpnd : RegisterOperand<FCC> {
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 201 def FCC#I : MipsReg<#I, "fcc"#I>;
425 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
708 def FCCRegsOpnd : RegisterOperand<FCC> {
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 201 def FCC#I : MipsReg<I, "fcc"#I>;
425 def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
708 def FCCRegsOpnd : RegisterOperand<FCC> {
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 60 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
356 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 61 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
356 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.td | 60 def FCC#I : SparcCtrlReg<I, "FCC"#I>;
356 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>;
|
| /external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/ |
| D | SpecialCasing.txt | 180 1FC3; 1FC3; 1FCC; 0397 0399; # GREEK SMALL LETTER ETA WITH YPOGEGRAMMENI
181 1FCC; 1FC3; 1FCC; 0397 0399; # GREEK CAPITAL LETTER ETA WITH PROSGEGRAMMENI
|
| /external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/ |
| D | SpecialCasing.txt | 180 1FC3; 1FC3; 1FCC; 0397 0399; # GREEK SMALL LETTER ETA WITH YPOGEGRAMMENI
181 1FCC; 1FC3; 1FCC; 0397 0399; # GREEK CAPITAL LETTER ETA WITH PROSGEGRAMMENI
|
| /external/icu/icu4c/source/data/unidata/ |
| D | SpecialCasing.txt | 180 1FC3; 1FC3; 1FCC; 0397 0399; # GREEK SMALL LETTER ETA WITH YPOGEGRAMMENI
181 1FCC; 1FC3; 1FCC; 0397 0399; # GREEK CAPITAL LETTER ETA WITH PROSGEGRAMMENI
|
| D | DerivedCoreProperties.txt | 735 1FC6..1FCC ; Alphabetic
2738 1FC6..1FCC ; Cased
3731 1FC8..1FCC ; Changes_When_Lowercased
4355 1FCC ; Changes_When_Uppercased
5608 1FC7..1FCC ; Changes_When_Casefolded
5883 1FC6..1FCC ; Changes_When_Casemapped
6216 1FC6..1FCC ; ID_Start
7212 1FC6..1FCC ; ID_Continue
8208 1FC6..1FCC ; XID_Start
9204 1FC6..1FCC ; XID_Continue
[all …]
|
| D | DerivedNormalizationProps.txt | 878 1FC6..1FCC ; NFD_QC; N
1306 1FC6..1FCC ; NFKD_QC; N
2280 1FC6..1FCC ; Expands_On_NFD
2571 1FC6..1FCC ; Expands_On_NFKD
3929 1FCC ; NFKC_CF; 03B7 03B9
4598 2FCC ; NFKC_CF; 9EFD
9325 1FC7..1FCC ; Changes_When_NFKC_Casefolded
|
| /external/capstone/arch/Mips/ |
| D | MipsGenRegisterInfo.inc | 1164 // FCC Register Class...
1165 static MCPhysReg FCC[] = {
1169 // FCC Bit set.
1632 { FCC, FCCBits, 157, 8, sizeof(FCCBits), Mips_FCCRegClassID, 4, 4, 1, 0 },
|
| /external/icu/android_icu4j/testing/src/android/icu/extratest/ |
| D | expected_transliteration_id_list_release_1.txt | 538 Any-FCC
|
| /external/icu/android_icu4j/src/main/tests/android/icu/extratest/ |
| D | expected_transliteration_id_list.txt | 549 Any-FCC
|
| /external/testng/doc/samplereport/css/ |
| D | maven-classic.css | 498 background-color: #FCC;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 2055 // FCC Register Class...
2056 const MCPhysReg FCC[] = {
2060 // FCC Bit set.
2688 { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 1, false },
3971 { 32, 32, 32, VTLists+0 }, // FCC
6408 { // FCC
7163 {0, 0}, // FCC
|
| /external/cldr/common/testData/localeIdentifiers/ |
| D | localeDisplayName.txt | 83 en-t-d0-fcc; English (To Unicode FCC)
|
| /external/icu/icu4c/source/data/lang/ |
| D | ar_XB.txt | 979 fcc{"To Unicode FCC"}
|