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Searched refs:FMAD (Results 1 – 25 of 44) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dfmad-formation-fmul-distribute-denormal-mode.ll8 …mdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,FMAD %s
9 …amdgcn -mcpu=verde -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,FMAD %s
10 …=amdgcn -mcpu=fiji -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,FMAD %s
11 …amdgcn -mcpu=tonga -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,FMAD %s
12 …mdgcn -mcpu=gfx900 -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN,FMAD %s
30 ; FMAD-LABEL: unsafe_fmul_fadd_distribute_fast_f32:
31 ; FMAD: ; %bb.0:
32 ; FMAD-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
33 ; FMAD-NEXT: v_mac_f32_e32 v0, v1, v0
34 ; FMAD-NEXT: s_setpc_b64 s[30:31]
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-fmad.s32.mir23 ; GFX6: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
24 ; GFX6: $vgpr0 = COPY [[FMAD]](s32)
29 ; GFX7: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
30 ; GFX7: $vgpr0 = COPY [[FMAD]](s32)
35 ; GFX101: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
36 ; GFX101: $vgpr0 = COPY [[FMAD]](s32)
66 ; GFX6: [[FMAD:%[0-9]+]]:_(s32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
67 ; GFX6: $vgpr0 = COPY [[FMAD]](s32)
72 ; GFX7: [[FMAD:%[0-9]+]]:_(s32) = nnan G_FMAD [[COPY]], [[COPY1]], [[COPY2]]
73 ; GFX7: $vgpr0 = COPY [[FMAD]](s32)
[all …]
Dlegalize-fmad.s16.mir41 ; GFX7: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC1]], [[TRUNC2]]
42 ; GFX7: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FMAD]](s16)
133 ; GFX7: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC2]], [[TRUNC4]]
135 ; GFX7: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FMAD]](s16)
292 ; GFX7: [[FMAD:%[0-9]+]]:_(s16) = G_FMAD [[TRUNC]], [[TRUNC4]], [[TRUNC8]]
296 ; GFX7: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FMAD]](s16)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h248 FMAD, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h360 FMAD, enumerator
DTargetLowering.h2533 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegalForFAddFSub()
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h464 FMAD, enumerator
DTargetLowering.h2702 return isOperationLegal(ISD::FMAD, N->getValueType(0)); in isFMADLegal()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCodeGenPrepare.cpp935 auto FMAD = !ST->hasMadMacF32Insts() in expandDivRem24Impl() local
938 Value *FR = Builder.CreateIntrinsic(FMAD, in expandDivRem24Impl()
DAMDGPUISelLowering.cpp587 case ISD::FMAD: in fnegFoldsIntoOp()
818 case ISD::FMAD: { in getNegatedExpression()
1719 (unsigned)ISD::FMAD : in LowerDIVREM24()
1803 unsigned FMAD = !Subtarget->hasMadMacF32Insts() ? in LowerUDIVREM64() local
1806 (unsigned)ISD::FMAD : in LowerUDIVREM64()
1811 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
1820 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
3714 case ISD::FMAD: { in performFNegCombine()
DSIISelLowering.cpp460 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
615 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
901 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
9312 case ISD::FMAD: in fp16SrcZerosHighBits()
9486 case ISD::FMAD: in isCanonicalized()
10197 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
10198 return ISD::FMAD; in getFusedOpcode()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp201 case ISD::FMAD: return "fmad"; in getOperationName()
DDAGCombiner.cpp7772 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFADDForFMACombine()
7789 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFADDForFMACombine()
7960 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFSUBForFMACombine()
7976 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFSUBForFMACombine()
8230 bool HasFMAD = (LegalOperations && TLI.isOperationLegal(ISD::FMAD, VT)); in visitFMULForFMACombine()
8242 unsigned PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA; in visitFMULForFMACombine()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp517 case ISD::FMAD: in fnegFoldsIntoOp()
1593 (unsigned)ISD::FMAD; in LowerDIVREM24()
1676 unsigned FMAD = MFI->getMode().FP32Denormals ? in LowerUDIVREM64() local
1678 (unsigned)ISD::FMAD; in LowerUDIVREM64()
1682 SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi, in LowerUDIVREM64()
1691 SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc, in LowerUDIVREM64()
3735 case ISD::FMAD: { in performFNegCombine()
DSIISelLowering.cpp382 setOperationAction(ISD::FMAD, MVT::f32, Legal); in SITargetLowering()
523 setOperationAction(ISD::FMAD, MVT::f16, Legal); in SITargetLowering()
782 return ((Opcode == ISD::FMAD && Subtarget->hasMadMixInsts()) || in isFPExtFoldable()
8598 case ISD::FMAD: in fp16SrcZerosHighBits()
8767 case ISD::FMAD: in isCanonicalized()
9444 isOperationLegal(ISD::FMAD, VT)) in getFusedOpcode()
9445 return ISD::FMAD; in getFusedOpcode()
DR600ISelLowering.cpp231 setOperationAction(ISD::FMAD, MVT::f32, Legal); in R600TargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp258 case ISD::FMAD: return "fmad"; in getOperationName()
/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp2946 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS); in PerformDAGCombine()
2955 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS); in PerformDAGCombine()
2984 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS); in PerformDAGCombine()
2994 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS); in PerformDAGCombine()
DAMDGPUISelLowering.cpp260 setOperationAction(ISD::FMAD, MVT::f32, Legal); in AMDGPUTargetLowering()
1293 SDValue fr = DAG.getNode(ISD::FMAD, DL, FltVT, fqneg, fb, fa); in LowerDIVREM24()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp262 case ISD::FMAD: return "fmad"; in getOperationName()
DLegalizeFloatTypes.cpp2245 case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break; in PromoteFloatResult()
2610 case ISD::FMAD: R = SoftPromoteHalfRes_FMAD(N); break; in SoftPromoteHalfResult()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp645 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp872 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp755 setOperationAction(ISD::FMAD, VT, Expand); in initActions()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td431 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;

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