| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-amdgcn.rsq.clamp.mir | 56 ; VI: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]
58 ; VI: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
|
| D | legalize-fminnum.mir | 54 ; SI: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
55 ; SI: $vgpr0 = COPY [[FMINNUM]](s32)
59 ; VI: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
60 ; VI: $vgpr0 = COPY [[FMINNUM]](s32)
64 ; GFX9: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
65 ; GFX9: $vgpr0 = COPY [[FMINNUM]](s32)
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-fp-min-max-intrinsics.ll | 10 ; CHECK: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[COPY1]]
11 ; CHECK: $s0 = COPY [[FMINNUM]](s32)
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 532 FMINNUM, FMAXNUM, enumerator
|
| D | BasicTTIImpl.h | 769 ISDs.push_back(ISD::FMINNUM); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 72 FUNCTION(minnum, 2, 0, experimental_constrained_minnum, FMINNUM)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2771 ISD = ISD::FMINNUM; in getMinMaxReductionCost()
2778 {ISD::FMINNUM, MVT::v4f32, 4}, in getMinMaxReductionCost()
2782 {ISD::FMINNUM, MVT::v2f64, 3}, in getMinMaxReductionCost()
2794 {ISD::FMINNUM, MVT::v4f32, 2}, in getMinMaxReductionCost()
2811 {ISD::FMINNUM, MVT::v4f32, 1}, in getMinMaxReductionCost()
2812 {ISD::FMINNUM, MVT::v4f64, 1}, in getMinMaxReductionCost()
2813 {ISD::FMINNUM, MVT::v8f32, 2}, in getMinMaxReductionCost()
2844 {ISD::FMINNUM, MVT::v8f64, 1}, in getMinMaxReductionCost()
2845 {ISD::FMINNUM, MVT::v16f32, 2}, in getMinMaxReductionCost()
2853 {ISD::FMINNUM, MVT::v4f32, 4}, in getMinMaxReductionCost()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 652 FMINNUM, FMAXNUM, enumerator
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 86 DAG_FUNCTION(minnum, 2, 0, experimental_constrained_minnum, FMINNUM)
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 825 FMINNUM, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 308 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
372 Opcode = ISD::FMINNUM; break; in mightUseCTR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 322 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
388 Opcode = ISD::FMINNUM; break; in mightUseCTR()
|
| /external/llvm-project/llvm/docs/GlobalISel/ |
| D | GenericOpcode.rst | 428 The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
444 definition. This differs from FMINNUM in the handling of signaling NaNs. If one
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 481 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
595 Opcode = ISD::FMINNUM; break; in mightUseCTR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 536 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
542 // The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
559 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 205 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
223 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
1709 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
2699 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
2816 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
2869 case ISD::FMINNUM: in PerformDAGCombine()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 2810 if (Entry.ISD == ISD::FMAXNUM || Entry.ISD == ISD::FMINNUM) { in getTypeBasedIntrinsicInstrCost()
3587 ISD = ISD::FMINNUM; in getMinMaxCost()
3591 {ISD::FMINNUM, MVT::v4f32, 1}, in getMinMaxCost()
3595 {ISD::FMINNUM, MVT::v2f64, 1}, in getMinMaxCost()
3612 {ISD::FMINNUM, MVT::v8f32, 1}, in getMinMaxCost()
3613 {ISD::FMINNUM, MVT::v4f64, 1}, in getMinMaxCost()
3632 {ISD::FMINNUM, MVT::v16f32, 1}, in getMinMaxCost()
3633 {ISD::FMINNUM, MVT::v8f64, 1}, in getMinMaxCost()
3719 ISD = ISD::FMINNUM; in getMinMaxReductionCost()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 153 case ISD::FMINNUM: return "fminnum"; in getOperationName()
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | GenericOpcodes.td | 706 // FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
712 // The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
729 // FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 413 setOperationAction(ISD::FMINNUM, MVT::f32, Custom); in SITargetLowering()
415 setOperationAction(ISD::FMINNUM, MVT::f64, Custom); in SITargetLowering()
602 setOperationAction(ISD::FMINNUM, MVT::f16, Custom); in SITargetLowering()
609 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand); in SITargetLowering()
657 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom); in SITargetLowering()
659 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom); in SITargetLowering()
722 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
4084 case ISD::FMINNUM: in LowerOperation()
5808 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
8622 case ISD::FMINNUM: in fp16SrcZerosHighBits()
[all …]
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 408 case ISD::FMINNUM: in LegalizeOp()
808 case ISD::FMINNUM: in Expand()
|
| D | SelectionDAGDumper.cpp | 184 case ISD::FMINNUM: return "fminnum"; in getOperationName()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 504 setOperationAction(ISD::FMINNUM, MVT::f32, Custom); in SITargetLowering()
506 setOperationAction(ISD::FMINNUM, MVT::f64, Custom); in SITargetLowering()
699 setOperationAction(ISD::FMINNUM, MVT::f16, Custom); in SITargetLowering()
706 setOperationAction(ISD::FMINNUM, MVT::v4f16, Expand); in SITargetLowering()
764 setOperationAction(ISD::FMINNUM, MVT::v2f16, Custom); in SITargetLowering()
766 setOperationAction(ISD::FMINNUM, MVT::v4f16, Custom); in SITargetLowering()
836 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
4566 case ISD::FMINNUM: in LowerOperation()
6475 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
9336 case ISD::FMINNUM: in fp16SrcZerosHighBits()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 182 case ISD::FMINNUM: return "fminnum"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 412 case ISD::FMINNUM: in LegalizeOp()
927 case ISD::FMINNUM: in Expand()
|