| /external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
| D | legalize-fshr.mir | 16 ; SI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
17 ; SI: $vgpr0 = COPY [[FSHR]](s32)
22 ; VI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
23 ; VI: $vgpr0 = COPY [[FSHR]](s32)
28 ; GFX9: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
29 ; GFX9: $vgpr0 = COPY [[FSHR]](s32)
50 ; SI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
52 ; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
61 ; VI: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[UV]], [[UV2]], [[UV4]](s32)
63 ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FSHR]](s32), [[FSHR1]](s32)
[all …]
|
| D | regbankselect-fshr.mir | 19 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY5]](s32)
38 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY4]](s32)
57 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY1]], [[COPY4]](s32)
76 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY4]], [[COPY2]](s32)
94 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY3]](s32)
112 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY3]], [[COPY2]](s32)
130 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY3]], [[COPY1]], [[COPY2]](s32)
147 ; CHECK: [[FSHR:%[0-9]+]]:vgpr(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 612 FSHR, enumerator
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 385 case ISD::FSHR: in LegalizeOp()
795 case ISD::FSHR: in Expand()
|
| D | SelectionDAGDumper.cpp | 251 case ISD::FSHR: return "fshr"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 221 case ISD::FSHR: in PromoteIntegerResult()
1153 bool IsFSHR = Opcode == ISD::FSHR; in PromoteIntRes_FunnelShift()
2172 case ISD::FSHR: in ExpandIntegerResult()
3442 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
3444 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
|
| D | LegalizeVectorTypes.cpp | 155 case ISD::FSHR: in ScalarizeVectorResult()
1008 case ISD::FSHR: in SplitVectorResult()
3010 case ISD::FSHR: in WidenVectorResult()
|
| D | DAGCombiner.cpp | 1665 case ISD::FSHR: return visitFunnelShift(N); in visit()
6718 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
6719 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
6728 TLI.isOperationLegalOrCustom(ISD::FSHR, VT)) { in MatchFunnelPosNeg()
6729 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg); in MatchFunnelPosNeg()
6750 bool HasFSHR = hasOperation(ISD::FSHR, VT); in MatchRotate()
6836 Res = DAG.getNode(HasFSHL ? ISD::FSHL : ISD::FSHR, DL, VT, LHSShiftArg, in MatchRotate()
6897 LExtOp0, RExtOp0, ISD::FSHL, ISD::FSHR, DL); in MatchRotate()
6903 RExtOp0, LExtOp0, ISD::FSHR, ISD::FSHL, DL); in MatchRotate()
|
| D | TargetLowering.cpp | 1674 case ISD::FSHR: { in SimplifyDemandedBits()
6248 unsigned RevOpcode = IsFSHL ? ISD::FSHR : ISD::FSHL; in expandFunnelShift()
7741 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
|
| D | LegalizeDAG.cpp | 1219 case ISD::FSHR: in LegalizeOp()
3534 case ISD::FSHR: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 247 case ISD::FSHR: return "fshr"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 389 case ISD::FSHR: in LegalizeOp()
914 case ISD::FSHR: in Expand()
|
| D | LegalizeIntegerTypes.cpp | 3110 Lo = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 1], Result[Part0], in ExpandIntRes_MULFIX()
3112 Hi = DAG.getNode(ISD::FSHR, dl, NVT, Result[Part0 + 2], Result[Part0 + 1], in ExpandIntRes_MULFIX()
|
| D | LegalizeDAG.cpp | 1199 case ISD::FSHR: in LegalizeOp()
3401 case ISD::FSHR: in ExpandNode()
|
| D | TargetLowering.cpp | 1540 case ISD::FSHR: { in SimplifyDemandedBits()
7256 SDValue Result = DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo, in expandFixedPointMul()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.h | 39 FSHR, enumerator
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 238 setOperationAction(ISD::FSHR, XLenVT, Legal); in RISCVTargetLowering()
242 setOperationAction(ISD::FSHR, MVT::i32, Custom); in RISCVTargetLowering()
1214 case ISD::FSHR: { in ReplaceNodeResults()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 652 setOperationAction(ISD::FSHR, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1424 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1425 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1557 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1558 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 762 setOperationAction(ISD::FSHR, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 370 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 373 def fshr : SDNode<"ISD::FSHR" , SDTIntShiftDOp>;
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 686 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
689 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
11058 case ISD::FSHR: return LowerFunnelShift(Op, DAG); in LowerOperation()
11154 case ISD::FSHR: in ReplaceNodeResults()
|