| /external/python/cpython2/Lib/plat-irix5/ |
| D | FILE.py | 155 FTRUNC = 0x0200 variable
219 FTRUNC = 0x0200 variable
|
| /external/python/cpython2/Lib/plat-irix6/ |
| D | FILE.py | 562 FTRUNC = 0x0200 variable
657 FTRUNC = 0x0200 variable
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
|
| D | BasicTTIImpl.h | 788 ISDs.push_back(ISD::FTRUNC); in getIntrinsicInstrCost()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 82 FUNCTION(trunc, 1, 0, experimental_constrained_trunc, FTRUNC)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 642 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
|
| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 97 DAG_FUNCTION(trunc, 1, 0, experimental_constrained_trunc, FTRUNC)
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 807 FTRUNC, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 304 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; in mightUseCTR()
368 Opcode = ISD::FTRUNC; break; in mightUseCTR()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 245 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
278 setOperationAction(ISD::FTRUNC, MVT::f64, Custom); in AMDGPUTargetLowering()
419 setOperationAction(ISD::FTRUNC, VT, Expand); in AMDGPUTargetLowering()
714 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
1287 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1597 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div); in LowerFREM()
1611 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
1731 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X); in LowerFROUND32()
1832 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2047 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFP64_TO_INT()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 314 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; in mightUseCTR()
384 Opcode = ISD::FTRUNC; break; in mightUseCTR()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 257 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
418 setOperationAction(ISD::FTRUNC, VT, Expand); in AMDGPUTargetLowering()
523 case ISD::FTRUNC: in fnegFoldsIntoOp()
1137 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
1582 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1690 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
2033 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div); in LowerFREM()
2047 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2173 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND_LegalFTRUNC()
2257 if (isOperationLegal(ISD::FTRUNC, VT)) in LowerFROUND()
[all …]
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 308 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
484 setOperationAction(ISD::FTRUNC, VT, Expand); in AMDGPUTargetLowering()
593 case ISD::FTRUNC: in fnegFoldsIntoOp()
1243 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
1707 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1819 SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2); in LowerUDIVREM64()
2101 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, VT, Div, Flags); in LowerFREM()
2115 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
2240 SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X); in LowerFROUND()
2272 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
[all …]
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 473 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; in mightUseCTR()
591 Opcode = ISD::FTRUNC; break; in mightUseCTR()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 162 case ISD::FTRUNC: return "ftrunc"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 105 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; in SoftenFloatResult()
1042 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; in ExpandFloatResult()
1884 case ISD::FTRUNC: R = PromoteFloatRes_UnaryOp(N); break; in PromoteFloatResult()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 550 ISD::FTRUNC}) { in NVPTXTargetLowering()
2117 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA); in LowerFROUND32()
2129 SDValue RoundedAForSmallA = DAG.getNode(ISD::FTRUNC, SL, VT, A); in LowerFROUND32()
2149 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA); in LowerFROUND64()
2161 DAG.getNode(ISD::FTRUNC, SL, VT, A); in LowerFROUND64()
|
| /external/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 534 ISD::FTRUNC}) { in NVPTXTargetLowering()
2100 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA); in LowerFROUND32()
2112 SDValue RoundedAForSmallA = DAG.getNode(ISD::FTRUNC, SL, VT, A); in LowerFROUND32()
2132 SDValue RoundedA = DAG.getNode(ISD::FTRUNC, SL, VT, AdjustedA); in LowerFROUND64()
2144 DAG.getNode(ISD::FTRUNC, SL, VT, A); in LowerFROUND64()
|
| /external/mesa3d/src/broadcom/compiler/ |
| D | v3d_compiler.h | 1145 VIR_A_ALU1(FTRUNC) in VIR_A_ALU2()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 201 case ISD::FTRUNC: return "ftrunc"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 123 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; in SoftenFloatResult()
1180 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; in ExpandFloatResult()
2122 case ISD::FTRUNC: in PromoteFloatResult()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 203 case ISD::FTRUNC: return "ftrunc"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 125 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; in SoftenFloatResult()
1221 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; in ExpandFloatResult()
2229 case ISD::FTRUNC: in PromoteFloatResult()
2594 case ISD::FTRUNC: in SoftPromoteHalfResult()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 99 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
192 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
|