| /external/llvm-project/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 210 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
219 FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures()
238 FeatureBits.flip(FB); in ToggleFeature()
239 return FeatureBits; in ToggleFeature()
243 FeatureBits ^= FB; in ToggleFeature()
244 return FeatureBits; in ToggleFeature()
249 SetImpliedBits(FeatureBits, FB, ProcFeatures); in SetFeatureBitsTransitively()
250 return FeatureBits; in SetFeatureBitsTransitively()
257 FeatureBits.reset(I); in ClearFeatureBitsTransitively()
258 ClearImpliedBits(FeatureBits, I, ProcFeatures); in ClearFeatureBitsTransitively()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 198 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
206 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures()
222 FeatureBits.flip(FB); in ToggleFeature()
223 return FeatureBits; in ToggleFeature()
227 FeatureBits ^= FB; in ToggleFeature()
228 return FeatureBits; in ToggleFeature()
233 SetImpliedBits(FeatureBits, FB, ProcFeatures); in SetFeatureBitsTransitively()
234 return FeatureBits; in SetFeatureBitsTransitively()
241 FeatureBits.reset(I); in ClearFeatureBitsTransitively()
242 ClearImpliedBits(FeatureBits, I, ProcFeatures); in ClearFeatureBitsTransitively()
[all …]
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| /external/llvm/lib/MC/ |
| D | MCSubtargetInfo.cpp | 28 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); in InitMCProcessorInfo()
36 FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures); in setDefaultFeatures()
54 FeatureBits.flip(FB); in ToggleFeature()
55 return FeatureBits; in ToggleFeature()
59 FeatureBits ^= FB; in ToggleFeature()
60 return FeatureBits; in ToggleFeature()
66 SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures); in ToggleFeature()
67 return FeatureBits; in ToggleFeature()
71 SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures); in ApplyFeatureFlag()
72 return FeatureBits; in ApplyFeatureFlag()
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| /external/llvm-project/llvm/lib/Target/RISCV/Utils/ |
| D | RISCVBaseInfo.cpp | 26 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, in computeTargetABI() argument
30 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI()
90 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument
91 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
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| D | RISCVBaseInfo.h | 256 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
273 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Utils/ |
| D | RISCVBaseInfo.cpp | 13 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, in computeTargetABI() argument
17 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in computeTargetABI()
74 void validate(const Triple &TT, const FeatureBitset &FeatureBits) { in validate() argument
75 if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) in validate()
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| D | RISCVBaseInfo.h | 202 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
216 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 89 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
107 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()
109 FeatureBits = FeatureBits_; in setFeatureBits()
113 return FeatureBits[Feature]; in hasFeature()
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| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 91 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
110 const FeatureBitset& getFeatureBits() const { return FeatureBits; } in getFeatureBits()
112 FeatureBits = FeatureBits_; in setFeatureBits()
116 return FeatureBits[Feature]; in hasFeature()
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| /external/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 46 FeatureBitset FeatureBits; // Feature bits for current CPU + FS variable
73 return FeatureBits; in getFeatureBits()
79 FeatureBits = FeatureBits_; in setFeatureBits()
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| /external/deqp/modules/glshared/ |
| D | glsRandomUniformBlockCase.hpp | 43 enum FeatureBits enum
|
| /external/deqp/external/vulkancts/modules/vulkan/ubo/ |
| D | vktRandomUniformBlockCase.hpp | 39 enum FeatureBits enum
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| /external/deqp/external/vulkancts/modules/vulkan/transform_feedback/ |
| D | vktTransformFeedbackRandomLayoutCase.hpp | 40 enum FeatureBits enum
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 62 const FeatureBitset &FeatureBits = in DecodeGPRRegisterClass() local
66 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
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| /external/llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 64 const FeatureBitset &FeatureBits = in DecodeGPRRegisterClass() local
68 bool IsRV32E = FeatureBits[RISCV::FeatureRV32E]; in DecodeGPRRegisterClass()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 597 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local
620 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
1960 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeHINTInstruction() local
1971 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2173 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local
2175 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2176 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4126 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
4129 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()
4149 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
[all …]
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 781 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
783 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
788 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
820 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 867 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
868 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
874 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
884 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMInstPrinter.cpp | 867 const FeatureBitset &FeatureBits = STI.getFeatureBits(); in printMSRMaskOperand() local
868 if (FeatureBits[ARM::FeatureMClass]) { in printMSRMaskOperand()
874 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) { in printMSRMaskOperand()
884 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops]) { in printMSRMaskOperand()
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| /external/llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 765 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local
792 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
2333 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeHINTInstruction() local
2344 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2546 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local
2548 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2549 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4533 const FeatureBitset &FeatureBits = in DecodeThumbTableBranch() local
4540 if (Rn == 13 && !FeatureBits[ARM::HasV8Ops]) S = MCDisassembler::SoftFail; in DecodeThumbTableBranch()
4676 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 764 const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits(); in AddThumbPredicate() local
791 if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0) in AddThumbPredicate()
2312 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeHINTInstruction() local
2323 if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0)) in DecodeHINTInstruction()
2525 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); in DecodeSETPANInstruction() local
2527 if (!FeatureBits[ARM::HasV8_1aOps] || in DecodeSETPANInstruction()
2528 !FeatureBits[ARM::HasV8Ops]) in DecodeSETPANInstruction()
4653 const FeatureBitset &FeatureBits = in DecodeMSRMask() local
4656 if (FeatureBits[ARM::FeatureMClass]) { in DecodeMSRMask()
4676 if (!(FeatureBits[ARM::HasV7Ops])) in DecodeMSRMask()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 171 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
172 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
173 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
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| /external/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 199 FeatureBitset FeatureBits = FeatureBitStack.pop_back_val(); in popFeatureBits() local
200 copySTI().setFeatureBits(FeatureBits); in popFeatureBits()
201 setAvailableFeatures(ComputeAvailableFeatures(FeatureBits)); in popFeatureBits()
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| /external/capstone/arch/ARM/ |
| D | ARMDisassembler.c | 4108 uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode); in DecodeMSRMask() local
4109 if (FeatureBits & ARM_FeatureMClass) { in DecodeMSRMask()
4129 if (!(FeatureBits & ARM_HasV7Ops)) in DecodeMSRMask()
4139 if (!(FeatureBits & ARM_HasV7Ops)) { in DecodeMSRMask()
4153 (!(FeatureBits & ARM_FeatureDSPThumb2) && (Mask & 1))) in DecodeMSRMask()
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| D | ARMInstPrinter.c | 1610 uint64_t FeatureBits = ARM_getFeatureBits(MI->csh->mode); in printMSRMaskOperand() local
1612 if (FeatureBits & ARM_FeatureMClass) { in printMSRMaskOperand()
1617 if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_FeatureDSPThumb2)) { in printMSRMaskOperand()
1633 if (Opcode == ARM_t2MSR_M && (FeatureBits & ARM_HasV7Ops)) { in printMSRMaskOperand()
|