| /external/llvm/lib/Target/AMDGPU/ |
| D | SIIntrinsics.td | 142 // Gather4 with comparison
150 // Gather4 with offsets
158 // Gather4 with comparison and offsets
|
| D | SIDefines.h | 44 Gather4 = 1 << 25 enumerator
|
| D | SIInstrInfo.h | 320 return MI.getDesc().TSFlags & SIInstrFlags::Gather4; in isGather4()
324 return get(Opcode).TSFlags & SIInstrFlags::Gather4; in isGather4()
|
| D | SIInstrFormats.td | 51 field bits<1> Gather4 = 0;
83 let TSFlags{25} = Gather4;
|
| D | SIInstrInfo.td | 3561 let Gather4 = 1;
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 62 field bit Gather4 = 0;
176 let TSFlags{37} = Gather4;
|
| D | MIMGInstructions.td | 35 bit Gather4 = 0;
52 "Gather4", "NumExtraArgs", "Gradients", "G16", "Coordinates",
694 let Gather4 = 1;
698 Gather4 = 1, hasPostISelHook = 0 in {
|
| D | SIDefines.h | 65 Gather4 = UINT64_C(1) << 37, enumerator
|
| D | SIInstrInfo.h | 496 return MI.getDesc().TSFlags & SIInstrFlags::Gather4; in isGather4()
500 return get(Opcode).TSFlags & SIInstrFlags::Gather4; in isGather4()
|
| D | AMDGPU.td | 238 "Image Gather4 D16 hardware bug"
|
| D | AMDGPUInstructionSelector.cpp | 1542 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in selectImageIntrinsic()
|
| D | SIISelLowering.cpp | 1083 if (!BaseOpcode->Gather4) { in getTgtMemIntrinsic()
6032 DMaskLanes = BaseOpcode->Gather4 ? 4 : countPopulation(DMask); in lowerImage()
6067 !(BaseOpcode->Gather4 && Subtarget->hasImageGather4D16Bug())) in lowerImage()
|
| D | AMDGPULegalizerInfo.cpp | 4080 if (BaseOpcode->Gather4) { in legalizeImageIntrinsic()
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/ |
| D | builder_mem.h | 110 void Gather4(const SWR_FORMAT format,
|
| D | builder_mem.cpp | 245 void Builder::Gather4(const SWR_FORMAT format, in Gather4() function in SwrJit::Builder
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 61 field bit Gather4 = 0;
167 let TSFlags{37} = Gather4;
|
| D | SIDefines.h | 64 Gather4 = UINT64_C(1) << 37, enumerator
|
| D | MIMGInstructions.td | 35 bit Gather4 = 0;
50 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4",
677 let Gather4 = 1;
681 Gather4 = 1, hasPostISelHook = 0 in {
|
| D | SIInstrInfo.h | 490 return MI.getDesc().TSFlags & SIInstrFlags::Gather4; in isGather4()
494 return get(Opcode).TSFlags & SIInstrFlags::Gather4; in isGather4()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.h | 210 bool Gather4; member
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.h | 202 bool Gather4; member
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 486 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; in convertMIMGInst()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 528 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; in convertMIMGInst()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2964 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : countPopulation(DMask); in validateMIMGDataSize()
3039 if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0) in validateMIMGGatherDMask()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 3233 (Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : countPopulation(DMask); in validateMIMGDataSize()
3311 if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0) in validateMIMGGatherDMask()
|