Searched refs:ID_AA64PFR0_ELX_MASK (Results 1 – 16 of 16) sorted by relevance
48 el_status &= ID_AA64PFR0_ELX_MASK; in socfpga_get_spsr_for_bl33_entry()
116 el_status &= ID_AA64PFR0_ELX_MASK; in marvell_get_spsr_for_bl33_entry()
47 cmp x1, #ID_AA64PFR0_ELX_MASK
69 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
67 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
66 el_status &= ID_AA64PFR0_ELX_MASK; in poplar_get_spsr_for_bl33_entry()
142 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
146 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
56 el_status &= ID_AA64PFR0_ELX_MASK; in sq_get_spsr_for_bl33_entry()
51 el_status &= ID_AA64PFR0_ELX_MASK; in k3_get_spsr_for_bl33_entry()
97 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
92 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
81 el_status &= ID_AA64PFR0_ELX_MASK; in get_spsr_for_bl33_entry()
572 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; in el_implemented()
164 #define ID_AA64PFR0_ELX_MASK ULL(0xf) macro