| /external/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 339 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
347 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
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| D | README_ALTIVEC.txt | 319 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 274 INSERT_VECTOR_ELT, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 782 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
815 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
823 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
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| D | README_ALTIVEC.txt | 319 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 386 INSERT_VECTOR_ELT, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 494 INSERT_VECTOR_ELT, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 214 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
215 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
216 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
217 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
281 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
737 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1887 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
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| D | SIISelLowering.cpp | 271 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
300 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
301 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
317 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering()
318 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f16, Custom); in SITargetLowering()
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); in SITargetLowering()
320 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f16, Custom); in SITargetLowering()
328 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i8, Custom); in SITargetLowering()
329 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i8, Custom); in SITargetLowering()
330 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i8, Custom); in SITargetLowering()
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 214 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
215 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
216 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
217 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
281 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
742 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1893 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
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| D | SIISelLowering.cpp | 303 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
332 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
333 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
346 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
347 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v8i32); in SITargetLowering()
360 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
361 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v16i32); in SITargetLowering()
374 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
375 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v32i32); in SITargetLowering()
391 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i16, Custom); in SITargetLowering()
[all …]
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 1011 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
1044 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
1052 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
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| D | README_ALTIVEC.txt | 314 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 171 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
172 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
173 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
174 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
199 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
910 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1996 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 430 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
434 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
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| D | LegalizeVectorTypes.cpp | 56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
837 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1417 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1421 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2692 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
2928 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], in CollectOpsToWiden()
3683 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
4731 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE()
4860 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 446 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
450 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
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| D | LegalizeVectorTypes.cpp | 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
602 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
989 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
993 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2064 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
2302 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], in WidenVecRes_BinaryCanTrap()
2832 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
3481 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
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| D | SelectionDAGDumper.cpp | 218 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeTypesGeneric.cpp | 435 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
439 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
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| D | LegalizeVectorTypes.cpp | 57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
893 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
1523 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
1527 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2846 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
3089 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in CollectOpsToWiden()
3836 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
4858 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE()
4883 Op = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WideVT, Op, NeutralElem, in WidenVecOp_VECREDUCE_SEQ()
5012 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
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| /external/llvm-project/llvm/utils/ |
| D | update_mir_test_checks.py | 258 INSERT_VECTOR_ELT='IVEC',
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 157 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1205 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
1731 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v2i64, Result, in LowerBUILD_VECTOR()
1764 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 155 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) { in WebAssemblyTargetLowering()
1018 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
1463 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 98 setOperationAction(ISD::INSERT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
189 setOperationAction(ISD::INSERT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
1566 case ISD::INSERT_VECTOR_ELT: return LowerHvxInsertElement(Op, DAG); in LowerHvxOperation()
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