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/external/llvm/test/MC/ARM/
Dv8_IT_manual.s11 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
14 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
18 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
30 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
34 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
42 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
46 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
50 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
59 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
71 @ CHECK: [[@LINE+2]]:1: warning: deprecated instruction in IT block
[all …]
Dthumb2-narrow-dp.ll24 IT EQ
28 IT EQ
33 IT EQ
37 IT EQ
50 IT EQ
52 ADDEQ r0, r2, r1 // (In IT) ADD has T1 narrow 3 operand
54 IT EQ
56 ADDEQ r2, r2, r1 // (In IT) ADD has T1 narrow 3 operand
59 IT EQ
63 IT EQ
[all …]
/external/llvm-project/llvm/test/MC/ARM/
Dv8_IT_manual.s11 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
14 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
18 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
30 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
34 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
42 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
46 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
50 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
59 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
71 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
[all …]
Dunpred-control-flow-in-it-block.s4 @ an IT block, but not the last instruction in the block.
8 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
10 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
12 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
16 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
18 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
20 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
24 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
26 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
28 …E-1]]:{{[0-9]+}}: error: instruction must be outside of IT block or the last instruction in an IT …
[all …]
Dthumb2-narrow-dp.ll24 IT EQ
28 IT EQ
33 IT EQ
37 IT EQ
50 IT EQ
52 ADDEQ r0, r2, r1 // (In IT) ADD has T1 narrow 3 operand
54 IT EQ
56 ADDEQ r2, r2, r1 // (In IT) ADD has T1 narrow 3 operand
59 IT EQ
63 IT EQ
[all …]
Dimplicit-it.s21 @ A single conditional instruction without IT block
28 @ THUMB-STDERR: error: predicated instructions must be in IT block
29 @ ARM-STDERR: warning: predicated instructions should be in IT block
31 @ A single conditional instruction with IT block
42 @ A single conditional instruction with IT block, but incorrect condition
47 @ THUMB-STDERR: error: incorrect condition in IT block
48 @ ARM-STDERR: error: incorrect condition in IT block
50 @ Multiple conditional instructions in an IT block, inverted and non-inverted conditions
66 @ Incorrectly inverted condition on the second slot of an IT block
72 @ THUMB-STDERR: error: incorrect condition in IT block
[all …]
Dit-nv.s4 @ CHECK-ERRS: error: unpredictable IT predicate sequence
6 @ CHECK-ERRS: error: unpredictable IT predicate sequence
8 @ CHECK-ERRS: error: unpredictable IT predicate sequence
10 @ CHECK-ERRS: error: unpredictable IT predicate sequence
12 @ CHECK-ERRS: error: unpredictable IT predicate sequence
/external/OpenCSD/decoder/tests/snapshots-ete/002-ack_test_scr/
Dtest_TARMAC3 1 clk cpu0 IT (1) 10300000 14004000 O EL3h_s : B 0x10310000
4 2 clk cpu0 IT (2) 10310000 d2b01000 O EL3h_s : MOV x0,#0x80800000
6 3 clk cpu0 IT (3) 10310004 d51e2040 O EL3h_s : MSR TCR_EL3,x0
8 4 clk cpu0 IT (4) 10310008 d5033fdf O EL3h_s : ISB
28 5 clk cpu0 IT (5) 1031000c d2b01000 O EL3h_s : MOV x0,#0x80800000
30 6 clk cpu0 IT (6) 10310010 d51c2040 O EL3h_s : MSR TCR_EL2,x0
32 7 clk cpu0 IT (7) 10310014 d5033fdf O EL3h_s : ISB
35 8 clk cpu0 IT (8) 10310018 d2800040 O EL3h_s : MOV x0,#2
37 9 clk cpu0 IT (9) 1031001c d51c1100 O EL3h_s : MSR HCR_EL2,x0
39 10 clk cpu0 IT (10) 10310020 d5033fdf O EL3h_s : ISB
[all …]
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/X86/
DSnippetGeneratorTest.cpp87 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
88 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
89 ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm. in TEST_F()
90 EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set"; in TEST_F()
110 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
111 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
112 ASSERT_THAT(IT.getVariableValues(), SizeIs(2)); in TEST_F()
113 EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set"; in TEST_F()
114 EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set"; in TEST_F()
132 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
[all …]
DTargetTest.cpp363 InstructionTemplate IT(&I); in TEST_F() local
365 State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset); in TEST_F()
367 EXPECT_THAT(IT.getValueFor(I.Operands[2]), IsReg(X86::RDI)); in TEST_F()
368 EXPECT_THAT(IT.getValueFor(I.Operands[3]), IsImm(1)); in TEST_F()
369 EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(0)); in TEST_F()
370 EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(kOffset)); in TEST_F()
371 EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0)); in TEST_F()
376 InstructionTemplate IT(&I); in TEST_F() local
378 State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset); in TEST_F()
380 EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI)); in TEST_F()
[all …]
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/PowerPC/
DSnippetGeneratorTest.cpp71 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
72 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
73 ASSERT_THAT(IT.getVariableValues(), SizeIs(3)); in TEST_F()
74 EXPECT_THAT(IT.getVariableValues(), in TEST_F()
101 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
102 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
103 ASSERT_THAT(IT.getVariableValues(), SizeIs(4)); in TEST_F()
104 EXPECT_THAT(IT.getVariableValues()[2], IsInvalid()) << "Operand 1 is not set"; in TEST_F()
105 EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set"; in TEST_F()
127 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
[all …]
/external/cldr/tools/java/org/unicode/cldr/util/data/external/
D2013-1_UNLOCODE_CodeListPart2.csv9540 ,"IN","BAU","IT-ITES-A-SEZ/Ulwe","IT-ITES-A-SEZ/Ulwe","MH","-----6--","RQ","1007",,"1815N 07326E",
9541 ,"IN","BAI","IT-ITES-B-SEZ/Ulwe","IT-ITES-B-SEZ/Ulwe","MH","-----6--","RQ","1007",,"1815N 07326E",
9542 ,"IN","BAT","IT-ITES-C-SEZ/Ulwe","IT-ITES-C-SEZ/Ulwe","MH","-----6--","AF","1101",,"1845N 07320E",
9543 ,"IN","KLN","IT-ITES-SEZ/Kalamboli","IT-ITES-SEZ/Kalamboli","MH","-----6--","AF","1101",,"1902N 073…
9821 ,"IN","CGI","MWCDL-IT-SEZ/Chengalpattu","MWCDL-IT-SEZ/Chengalpattu","TN","-----6--","RQ","1001",,"1…
10559 ,"IT",,".ITALY",,,"",,,,,
10560 ,"IT","AOM","Abano Terme","Abano Terme","PD","--3-----","RQ","1001",,"4521N 01147E",
10561 ,"IT","BBD","Abbadia Lariana","Abbadia Lariana","LC","-----6--","RL","1201",,"4554N 00920E",
10562 ,"IT","GBB","Abbiate Guazzone","Abbiate Guazzone",,"--3-----","RL","0901",,"4541N 00855E",
10563 ,"IT","ATR","Abbiategrasso","Abbiategrasso",,"--3-----","RL","0201",,"4524N 00854E",
[all …]
DsubdivisionData.txt2114 region IT-67 Molise it
2115 province IT-IS Isernia it IT-67
2116 province IT-CB Campobasso it IT-67
2117 region IT-23 Val d'Aoste fr
2118 region IT-23 Valle d'Aosta it
2119 province IT-AO Aoste fr IT-23
2120 province IT-AO Aosta it IT-23
2121 region IT-25 Lombardia it
2122 province IT-CR Cremona it IT-25
2123 province IT-LC Lecco it IT-25
[all …]
/external/llvm-project/clang-tools-extra/clang-doc/
DRepresentation.h122 Reference(SymbolID USR, StringRef Name, InfoType IT) in Reference()
123 : USR(USR), Name(Name), RefType(IT) {} in Reference()
126 Reference(SymbolID USR, StringRef Name, InfoType IT, StringRef Path) in Reference()
127 : USR(USR), Name(Name), RefType(IT), Path(Path), in Reference()
160 TypeInfo(SymbolID Type, StringRef Field, InfoType IT) in TypeInfo()
161 : Type(Type, Field, IT) {} in TypeInfo()
162 TypeInfo(SymbolID Type, StringRef Field, InfoType IT, StringRef Path) in TypeInfo()
163 : Type(Type, Field, IT, Path) {} in TypeInfo()
175 FieldTypeInfo(SymbolID Type, StringRef Field, InfoType IT, StringRef Path, in FieldTypeInfo()
177 : TypeInfo(Type, Field, IT, Path), Name(Name) {} in FieldTypeInfo()
[all …]
/external/llvm-project/llvm/tools/llvm-exegesis/lib/PowerPC/
DTarget.cpp17 static void setMemOp(InstructionTemplate &IT, int OpIdx, in setMemOp() argument
19 const auto Op = IT.getInstr().Operands[OpIdx]; in setMemOp()
21 IT.getValueFor(Op) = OpVal; in setMemOp()
38 void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
73 void ExegesisPowerPCTarget::fillMemoryOperands(InstructionTemplate &IT, in fillMemoryOperands() argument
77 if (IT.getInstr().hasTiedRegisters()) in fillMemoryOperands()
80 const auto DispOp = IT.getInstr().Operands[DispOpIdx]; in fillMemoryOperands()
85 setMemOp(IT, DispOpIdx, MCOperand::createReg(PPC::X1)); in fillMemoryOperands()
87 setMemOp(IT, DispOpIdx, MCOperand::createImm(Offset)); // Disp in fillMemoryOperands()
88 setMemOp(IT, MemOpIdx + 2, MCOperand::createReg(Reg)); // BaseReg in fillMemoryOperands()
/external/llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/
DSnippetGeneratorTest.cpp71 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
72 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
73 ASSERT_THAT(IT.getVariableValues(), SizeIs(3)); in TEST_F()
74 EXPECT_THAT(IT.getVariableValues(), in TEST_F()
119 const InstructionTemplate &IT = CT.Instructions[0]; in TEST_F() local
120 EXPECT_THAT(IT.getOpcode(), Opcode); in TEST_F()
121 ASSERT_THAT(IT.getVariableValues(), SizeIs(3)); in TEST_F()
122 EXPECT_EQ(IT.getVariableValues()[0].getReg(), 0u); in TEST_F()
123 EXPECT_EQ(IT.getVariableValues()[2].getImm(), 0); in TEST_F()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/Mips/
DTarget.cpp42 static void setMemOp(InstructionTemplate &IT, int OpIdx, in setMemOp() argument
44 const auto Op = IT.getInstr().Operands[OpIdx]; in setMemOp()
46 IT.getValueFor(Op) = OpVal; in setMemOp()
59 void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
137 void ExegesisMipsTarget::fillMemoryOperands(InstructionTemplate &IT, in fillMemoryOperands() argument
140 assert(!isInvalidMemoryInstr(IT.getInstr()) && in fillMemoryOperands()
142 setMemOp(IT, 0, MCOperand::createReg(0)); // IndexReg in fillMemoryOperands()
143 setMemOp(IT, 1, MCOperand::createReg(Reg)); // BaseReg in fillMemoryOperands()
144 setMemOp(IT, 2, MCOperand::createImm(Offset)); // Disp in fillMemoryOperands()
/external/llvm-project/libcxx/test/std/utilities/tuple/tuple.tuple/tuple.cnstr/
DPR27684_contains_ref_to_incomplete_type.pass.cpp35 using IT = IncompleteType; in main() typedef
37 using Tup = std::tuple<const IT&, const IT&>; in main()
43 using Tup = std::tuple<const IT&, const IT&>; in main()
/external/libcxx/test/std/utilities/tuple/tuple.tuple/tuple.cnstr/
DPR27684_contains_ref_to_incomplete_type.pass.cpp34 using IT = IncompleteType; in main() typedef
36 using Tup = std::tuple<const IT&, const IT&>; in main()
42 using Tup = std::tuple<const IT&, const IT&>; in main()
/external/llvm-project/llvm/tools/llvm-exegesis/lib/
DSnippetGenerator.cpp78 for (InstructionTemplate &IT : CT.Instructions) { in generateConfigurations()
79 if (auto error = randomizeUnsetVariables(State, ForbiddenRegs, IT)) in generateConfigurations()
81 BC.Key.Instructions.push_back(IT.build()); in generateConfigurations()
108 for (const InstructionTemplate &IT : Instructions) { in computeRegisterInitialValues() local
111 const auto GetOpReg = [&IT](const Operand &Op) -> unsigned { in computeRegisterInitialValues()
116 if (Op.isExplicit() && IT.getValueFor(Op).isReg()) in computeRegisterInitialValues()
117 return IT.getValueFor(Op).getReg(); in computeRegisterInitialValues()
121 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
131 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues()
263 InstructionTemplate &IT) { in randomizeUnsetVariables() argument
[all …]
DParallelSnippetGenerator.cpp102 for (InstructionTemplate &IT : Instructions) { in instantiateMemoryOperands()
103 ET.fillMemoryOperands(IT, ScratchSpacePointerInReg, I * MemStep); in instantiateMemoryOperands()
108 InstructionTemplate IT = Instructions[I % OriginalInstructionsSize]; in instantiateMemoryOperands() local
109 ET.fillMemoryOperands(IT, ScratchSpacePointerInReg, I * MemStep); in instantiateMemoryOperands()
111 Instructions.push_back(std::move(IT)); in instantiateMemoryOperands()
118 const LLVMState &State, const InstructionTemplate &IT, in generateSnippetUsingStaticRenaming() argument
127 const Operand &Op = IT.getInstr().getPrimaryOperand(*Var); in generateSnippetUsingStaticRenaming()
135 InstructionTemplate TmpIT = IT; in generateSnippetUsingStaticRenaming()
/external/llvm/lib/Support/
DOptions.cpp21 for (auto IT = Options.begin(); IT != Options.end(); ++IT) in ~OptionRegistry() local
22 delete IT->second; in ~OptionRegistry()
/external/llvm-project/llvm/include/llvm/ADT/
Dilist.h251 pointer remove(iterator &IT) {
252 pointer Node = &*IT++;
258 pointer remove(const iterator &IT) {
259 iterator MutIt = IT;
263 pointer remove(pointer IT) { return remove(iterator(IT)); }
264 pointer remove(reference IT) { return remove(iterator(IT)); }
272 iterator erase(pointer IT) { return erase(iterator(IT)); }
273 iterator erase(reference IT) { return erase(iterator(IT)); }
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/
Dilist.h249 pointer remove(iterator &IT) {
250 pointer Node = &*IT++;
256 pointer remove(const iterator &IT) {
257 iterator MutIt = IT;
261 pointer remove(pointer IT) { return remove(iterator(IT)); }
262 pointer remove(reference IT) { return remove(iterator(IT)); }
270 iterator erase(pointer IT) { return erase(iterator(IT)); }
271 iterator erase(reference IT) { return erase(iterator(IT)); }
/external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/
Dilist.h264 pointer remove(iterator &IT) {
265 pointer Node = &*IT++;
271 pointer remove(const iterator &IT) {
272 iterator MutIt = IT;
276 pointer remove(pointer IT) { return remove(iterator(IT)); }
277 pointer remove(reference IT) { return remove(iterator(IT)); }
285 iterator erase(pointer IT) { return erase(iterator(IT)); }
286 iterator erase(reference IT) { return erase(iterator(IT)); }

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