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Searched refs:IntVT (Results 1 – 25 of 53) sorted by relevance

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/external/llvm-project/llvm/unittests/CodeGen/
DAArch64SelectionDAGTest.cpp125 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
126 auto VecVT = EVT::getVectorVT(Context, IntVT, 3); in TEST_F()
168 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
169 auto VecVT = EVT::getVectorVT(Context, IntVT, 3); in TEST_F()
185 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
186 auto VecVT = EVT::getVectorVT(Context, IntVT, 3); in TEST_F()
260 auto IntVT = EVT::getIntegerVT(Context, 8); in TEST_F() local
261 auto UnknownOp = DAG->getRegister(0, IntVT); in TEST_F()
262 auto Mask = DAG->getConstant(0x8A, Loc, IntVT); in TEST_F()
263 auto N0 = DAG->getNode(ISD::AND, Loc, IntVT, Mask, UnknownOp); in TEST_F()
[all …]
/external/llvm-project/llvm/lib/Target/VE/
DVEISelLowering.cpp153 for (MVT IntVT : {MVT::i32, MVT::i64}) { in initSPUActions()
155 setOperationAction(ISD::UREM, IntVT, Expand); in initSPUActions()
156 setOperationAction(ISD::SREM, IntVT, Expand); in initSPUActions()
157 setOperationAction(ISD::SDIVREM, IntVT, Expand); in initSPUActions()
158 setOperationAction(ISD::UDIVREM, IntVT, Expand); in initSPUActions()
161 setOperationAction(ISD::SHL_PARTS, IntVT, Expand); in initSPUActions()
162 setOperationAction(ISD::SRA_PARTS, IntVT, Expand); in initSPUActions()
163 setOperationAction(ISD::SRL_PARTS, IntVT, Expand); in initSPUActions()
167 setOperationAction(ISD::MULHU, IntVT, Expand); in initSPUActions()
168 setOperationAction(ISD::MULHS, IntVT, Expand); in initSPUActions()
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/external/llvm/include/llvm/CodeGen/
DValueTypes.h296 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
297 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
298 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.h346 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
347 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
348 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.h387 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
388 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
389 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp427 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
429 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
431 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
432 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DFastISel.cpp425 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
426 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
434 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1729 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1730 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1733 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1739 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1740 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1744 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
DTargetLowering.cpp6048 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local
6049 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT()
6051 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
6052 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
6053 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
6054 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); in expandFP_TO_SINT()
6055 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); in expandFP_TO_SINT()
6056 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
6058 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT()
6061 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
DLegalizeDAG.cpp1516 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1517 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1518 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1527 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1528 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1542 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1577 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
1578 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT); in ExpandFABS()
1579 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue, in ExpandFABS()
DLegalizeFloatTypes.cpp891 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in SoftenFloatOp_FP_TO_XINT() local
892 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in SoftenFloatOp_FP_TO_XINT()
893 ++IntVT) { in SoftenFloatOp_FP_TO_XINT()
894 NVT = (MVT::SimpleValueType)IntVT; in SoftenFloatOp_FP_TO_XINT()
DDAGCombiner.cpp11427 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
11428 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
11429 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
13400 EVT IntVT = Int.getValueType(); in visitFNEG() local
13401 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
13407 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
13410 SignMask = APInt::getSignMask(IntVT.getSizeInBits()); in visitFNEG()
13413 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int, in visitFNEG()
13414 DAG.getConstant(SignMask, DL0, IntVT)); in visitFNEG()
13497 EVT IntVT = Int.getValueType(); in visitFABS() local
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp438 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
440 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
442 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
443 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DFastISel.cpp439 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
440 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
448 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1796 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1797 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1800 Register IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1806 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*Op0IsKill=*/true, in selectFNeg()
1807 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1811 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
DTargetLowering.cpp6394 EVT IntVT = SrcVT.changeTypeToInteger(); in expandFP_TO_SINT() local
6395 EVT IntShVT = getShiftAmountTy(IntVT, DAG.getDataLayout()); in expandFP_TO_SINT()
6397 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
6398 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
6399 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
6400 SDValue SignMask = DAG.getConstant(APInt::getSignMask(SrcEltBits), dl, IntVT); in expandFP_TO_SINT()
6401 SDValue SignLowBit = DAG.getConstant(SrcEltBits - 1, dl, IntVT); in expandFP_TO_SINT()
6402 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
6404 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Src); in expandFP_TO_SINT()
6407 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
DLegalizeDAG.cpp1547 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1548 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1549 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1558 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1559 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1573 EVT ShiftVT = IntVT; in ExpandFCOPYSIGN()
1601 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFNEG() local
1604 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFNEG()
1606 DAG.getNode(ISD::XOR, DL, IntVT, SignAsInt.IntValue, SignMask); in ExpandFNEG()
1626 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DFunctionLoweringInfo.cpp430 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
432 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
434 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
435 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
DTargetLowering.cpp3097 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), in expandFP_TO_SINT() local
3099 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); in expandFP_TO_SINT()
3100 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); in expandFP_TO_SINT()
3101 SDValue Bias = DAG.getConstant(127, dl, IntVT); in expandFP_TO_SINT()
3103 IntVT); in expandFP_TO_SINT()
3104 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); in expandFP_TO_SINT()
3105 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); in expandFP_TO_SINT()
3107 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
3111 ISD::SRL, dl, IntVT, DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
3112 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT, DL))); in expandFP_TO_SINT()
[all …]
DFastISel.cpp233 EVT IntVT = TLI.getPointerTy(DL); in materializeConstant() local
236 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
246 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1496 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1497 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1500 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1506 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1507 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1511 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
DLegalizeDAG.cpp1442 EVT IntVT = SignAsInt.IntValue.getValueType(); in ExpandFCOPYSIGN() local
1443 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT); in ExpandFCOPYSIGN()
1444 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue, in ExpandFCOPYSIGN()
1453 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit, in ExpandFCOPYSIGN()
1454 DAG.getConstant(0, DL, IntVT), ISD::SETNE); in ExpandFCOPYSIGN()
1470 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1471 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1473 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); in ExpandFCOPYSIGN()
1474 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); in ExpandFCOPYSIGN()
1507 EVT IntVT = ValueAsInt.IntValue.getValueType(); in ExpandFABS() local
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DDAGCombiner.cpp7680 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
7681 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
7682 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
9308 EVT IntVT = Int.getValueType(); in visitFNEG() local
9309 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
9315 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
9318 SignMask = APInt::getSignBit(IntVT.getSizeInBits()); in visitFNEG()
9321 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int, in visitFNEG()
9322 DAG.getConstant(SignMask, DL0, IntVT)); in visitFNEG()
9413 EVT IntVT = Int.getValueType(); in visitFABS() local
[all …]
DLegalizeFloatTypes.cpp898 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in SoftenFloatOp_FP_TO_XINT() local
899 IntVT <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; in SoftenFloatOp_FP_TO_XINT()
900 ++IntVT) { in SoftenFloatOp_FP_TO_XINT()
901 NVT = (MVT::SimpleValueType)IntVT; in SoftenFloatOp_FP_TO_XINT()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1484 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
1496 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
4174 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local
4190 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, in lowerIntrinsicLoad()
4851 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local
4858 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT()
4867 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT()
4868 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
4869 DAG.getConstant(0xffff, SL, IntVT), in lowerINSERT_VECTOR_ELT()
4872 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1692 EVT IntVT = MemVT.changeTypeToInteger(); in lowerKernargMemParameter() local
1704 SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, SL, IntVT, Extract); in lowerKernargMemParameter()
4685 EVT IntVT = LoadVT.changeTypeToInteger(); in lowerIntrinsicLoad() local
4701 return getMemIntrinsicNode(Opc, DL, M->getVTList(), Ops, IntVT, in lowerIntrinsicLoad()
5438 MVT IntVT = MVT::getIntegerVT(VecSize); in lowerINSERT_VECTOR_ELT() local
5445 SDValue ExtVal = DAG.getNode(ISD::BITCAST, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5454 SDValue BCVec = DAG.getNode(ISD::BITCAST, SL, IntVT, Vec); in lowerINSERT_VECTOR_ELT()
5455 SDValue BFM = DAG.getNode(ISD::SHL, SL, IntVT, in lowerINSERT_VECTOR_ELT()
5456 DAG.getConstant(0xffff, SL, IntVT), in lowerINSERT_VECTOR_ELT()
5459 SDValue LHS = DAG.getNode(ISD::AND, SL, IntVT, BFM, ExtVal); in lowerINSERT_VECTOR_ELT()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp615 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits()); in initActions() local
616 if (IntVT.isValid()) { in initActions()
618 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp725 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); in initActions() local
726 if (IntVT.isValid()) { in initActions()
728 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); in initActions()

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