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Searched refs:MIDR_PN_SHIFT (Results 1 – 12 of 12) sorted by relevance

/external/arm-trusted-firmware/include/lib/cpus/aarch32/
Dcpu_macros.S17 (MIDR_PN_MASK << MIDR_PN_SHIFT)
224 ubfx r0, r0, #MIDR_PN_SHIFT, #12
225 ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
/external/arm-trusted-firmware/plat/imx/common/
Dimx8_helpers.S33 ubfx x0, x0, MIDR_PN_SHIFT, #12
34 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
/external/arm-trusted-firmware/include/lib/cpus/aarch64/
Dcpu_macros.S14 (MIDR_PN_MASK << MIDR_PN_SHIFT)
301 ubfx x0, x0, MIDR_PN_SHIFT, #12
302 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
/external/arm-trusted-firmware/plat/rockchip/common/aarch64/
Dplat_helpers.S36 ubfx x0, x0, MIDR_PN_SHIFT, #12
37 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
/external/arm-trusted-firmware/lib/cpus/aarch64/
Dcpuamu.c26 (MIDR_PN_MASK << MIDR_PN_SHIFT); in midr_match()
/external/arm-trusted-firmware/plat/renesas/common/include/
Drcar_def.h273 #define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT)
274 #define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT)
/external/arm-trusted-firmware/plat/renesas/common/aarch64/
Dplat_helpers.S348 ubfx x1, x0, MIDR_PN_SHIFT, #12
349 cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
/external/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/
Dtegra_helpers.S65 mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
67 lsr x0, x0, #MIDR_PN_SHIFT
/external/arm-trusted-firmware/plat/renesas/rzg/
Dbl2_plat_setup.c625 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
/external/arm-trusted-firmware/plat/renesas/rcar/
Dbl2_plat_setup.c743 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
/external/arm-trusted-firmware/include/arch/aarch32/
Darch.h22 #define MIDR_PN_SHIFT U(4) macro
/external/arm-trusted-firmware/include/arch/aarch64/
Darch.h25 #define MIDR_PN_SHIFT U(0x4) macro