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Searched refs:MIs (Results 1 – 25 of 47) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
111 if ((size_t)NewInsnID < State.MIs.size()) in executeMatchTable()
112 State.MIs[NewInsnID] = NewMI; in executeMatchTable()
114 assert((size_t)NewInsnID == State.MIs.size() && in executeMatchTable()
116 State.MIs.push_back(NewMI); in executeMatchTable()
143 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
144 unsigned Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
163 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
164 const int64_t Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
191 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
[all …]
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h62 bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException(); in executeMatchTable()
64 const uint16_t Flags = State.MIs[0]->getFlags(); in executeMatchTable()
112 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
129 if ((size_t)NewInsnID < State.MIs.size()) in executeMatchTable()
130 State.MIs[NewInsnID] = NewMI; in executeMatchTable()
132 assert((size_t)NewInsnID == State.MIs.size() && in executeMatchTable()
134 State.MIs.push_back(NewMI); in executeMatchTable()
165 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
166 unsigned Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
188 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGICombiner.inc122 SmallVector<MachineInstr *, 8> MIs = { &MI };
133 switch (MIs[0]->getOpcode()) {
150 return Helper.matchCombineCopy(*MIs[0]);
153 Helper.applyCombineCopy(*MIs[0]);
165 return Helper.matchPtrAddImmedChain(*MIs[0], MatchData1);
168 Helper.applyPtrAddImmedChain(*MIs[0], MatchData1);
180 return Helper.matchCombineExtendingLoads(*MIs[0], MatchData2);
183 Helper.applyCombineExtendingLoads(*MIs[0], MatchData2);
192 return Helper.matchCombineIndexedLoadStore(*MIs[0], MatchData3);
195 Helper.applyCombineIndexedLoadStore(*MIs[0], MatchData3);
[all …]
DAArch64GenGlobalISel.inc1131 State.MIs.clear();
1132 State.MIs.push_back(&I);
1363 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1369 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1372 // MIs[2] Rn
1388 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1394 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
1397 // MIs[2] Rn
1427 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1431 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
[all …]
/external/llvm-project/llvm/test/TableGen/
DGlobalISelEmitterCustomPredicate.td54 // CHECK-NEXT: // MIs[0] dst
57 // CHECK-NEXT: // MIs[0] src2
61 // CHECK-NEXT: // MIs[0] Operand 2
63 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
66 // CHECK-NEXT: // MIs[1] Operand 0
68 // CHECK-NEXT: // MIs[1] src0
72 // CHECK-NEXT: // MIs[1] src1
84 // CHECK-NEXT: // MIs[0] dst
87 // CHECK-NEXT: // MIs[0] Operand 1
89 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
[all …]
DGlobalISelEmitter.td222 // CHECK-NEXT: State.MIs.clear();
223 // CHECK-NEXT: State.MIs.push_back(&I);
252 // R19N-NEXT: // MIs[0] dst
255 // R19N-NEXT: // MIs[0] src1
258 // R19N-NEXT: // MIs[0] complex_rr:src2a:src2b
262 // R19N-NEXT: // MIs[0] Operand 3
264 // R19C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
267 // R19N-NEXT: // MIs[1] Operand 0
269 // R19N-NEXT: // MIs[1] src3
274 // R19N-NEXT: // MIs[1] src4
[all …]
DGlobalISelEmitter-immAllZeroOne.td26 // GISEL-NOOPT: // MIs[0] Operand 2
28 // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
31 // GISEL-NOOPT-NEXT: // MIs[1] Operand 0
41 // GISEL-NOOPT: // MIs[0] Operand 2
43 // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46 // GISEL-NOOPT-NEXT: // MIs[1] Operand 0
Dgisel-physreg-input.td30 // GISEL-NEXT: // MIs[0] dst
33 // GISEL-NEXT: // MIs[0] src0
36 // GISEL-NEXT: // MIs[0] Operand 2
58 // GISEL-NEXT: // MIs[0] dst
61 // GISEL-NEXT: // MIs[0] SPECIAL
64 // GISEL-NEXT: // MIs[0] Operand 2
DGlobalISelEmitter-immarg-literal-pattern.td27 // GISEL-NEXT: // MIs[0] Operand 1
36 // GISEL-NEXT: // MIs[0] Operand 1
47 // GISEL-NEXT: // MIs[0] Operand 2
56 // GISEL-NEXT: // MIs[0] Operand 2
DContextlessPredicates.td29 // CHECK_NOPT-NEXT: // MIs[0] dst
32 // CHECK_NOPT-NEXT: // MIs[0] ptr
35 // CHECK_NOPT-NEXT: // MIs[0] val
60 // CHECK_OPT-NEXT: // MIs[0] ptr
DGlobalISelEmitter-atomic_store.td14 // GISEL-NEXT: // MIs[0] ptr
16 // GISEL-NEXT: // MIs[0] val
Dimmarg.td12 // GISEL-NEXT: // MIs[0] Operand 0
14 // GISEL-NEXT: // MIs[0] src
DGlobalISelEmitter-zero-reg.td27 // CHECK-NEXT: // MIs[0] dst
30 // CHECK-NEXT: // MIs[0] src
DGlobalISelEmitter-nested-subregs.td35 // CHECK-NEXT: // MIs[0] dst
38 // CHECK-NEXT: // MIs[0] src
DGlobalISelEmitterMatchTableOptimizer.td16 // CHECK-NEXT: // MIs[0] src
26 // CHECK-NEXT: // MIs[0] src
55 // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
DGlobalISelEmitterRegSequence.td35 // CHECK-NEXT: // MIs[0] dst
38 // CHECK-NEXT: // MIs[0] src
/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp238 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
239 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); in RemoveMI()
243 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
244 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); in RemoveMI()
301 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
303 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp254 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
255 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
259 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
260 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
317 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
319 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp258 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
259 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
263 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
264 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
321 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
323 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc659 State.MIs.clear();
660 State.MIs.push_back(&I);
744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
749 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
752 // MIs[2] Operand 1
772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
777 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
780 // MIs[2] Operand 1
799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
802 // MIs[1] Operand 1
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DVirtRegMap.cpp407 SmallVector<MachineInstr *, 2> MIs({&MI}); in expandCopyBundle() local
416 MIs.push_back(&*I); in expandCopyBundle()
418 MachineInstr *FirstMI = MIs.back(); in expandCopyBundle()
434 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) { in expandCopyBundle()
436 if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) { in expandCopyBundle()
438 std::swap(MIs[I], MIs[E - 1]); in expandCopyBundle()
449 for (MachineInstr *BundledMI : llvm::reverse(MIs)) { in expandCopyBundle()
/external/llvm-project/llvm/lib/CodeGen/
DVirtRegMap.cpp407 SmallVector<MachineInstr *, 2> MIs({&MI}); in expandCopyBundle() local
416 MIs.push_back(&*I); in expandCopyBundle()
418 MachineInstr *FirstMI = MIs.back(); in expandCopyBundle()
434 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) { in expandCopyBundle()
436 if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) { in expandCopyBundle()
438 std::swap(MIs[I], MIs[E - 1]); in expandCopyBundle()
449 for (MachineInstr *BundledMI : llvm::reverse(MIs)) { in expandCopyBundle()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc827 State.MIs.clear();
828 State.MIs.push_back(&I);
911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
983 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1008 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1032 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1056 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1080 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc783 State.MIs.clear();
784 State.MIs.push_back(&I);
888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
890 // MIs[1] Operand 1
958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
961 // MIs[1] Operand 1
975 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
977 // MIs[1] Operand 1
1045 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1048 // MIs[1] Operand 1
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DInstructionSelector.cpp32 : Renderers(MaxRenderers), MIs() {} in MatcherState()

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