| /external/mesa3d/src/mesa/x86/ |
| D | 3dnow_xform4.S | 98 MOVQ ( MM6, MM7 ) /* x3 | x3 */
106 PFMUL ( REGOFF(56, ECX), MM7 ) /* x3*m15 | x3*m14 */
109 PFADD ( MM5, MM7 )
112 PFADD ( MM3, MM7 )
115 MOVQ ( MM7, REGOFF(-8, EDX) )
166 PXOR ( MM7, MM7 ) /* 0 | 0 */
187 PFSUBR ( MM7, MM3 ) /* | -x2 */
239 MOVD ( REGOFF(40, ECX), MM7 ) /* | m10 */
240 PUNPCKLDQ ( REGOFF(56, ECX), MM7 ) /* m14 | m10 */
275 PFMUL ( MM7, MM5 ) /* x3*m14 | x2*m10 */
[all …]
|
| D | 3dnow_xform2.S | 82 MOVQ ( MM6, MM7 ) /* x1 | x0 */
85 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
87 PFACC ( MM7, MM6 ) /* x0*m01+x1*m11 | x0*x00+x1*m10 */
93 MOVQ ( MM6, MM7 ) /* x1 | x0 */
96 PFMUL ( MM3, MM7 ) /* x1*m13 | x0*m03 */
99 PFACC ( MM7, MM6 ) /* x0*m03+x1*m13 | x0*x02+x1*m12 */
216 MOVQ ( MM6, MM7 ) /* x1 | x0 */
219 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
221 PFACC ( MM7, MM6 ) /* x0*m01+x1*m11 | x0*x00+x1*m10 */
227 MOVQ ( MM6, MM7 ) /* x1 | x0 */
[all …]
|
| D | mmx_blend.S | 322 MOVQ ( REGIND(ESP), MM7 ) ;\
329 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
330 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
354 MOVQ ( REGIND(ESP), MM7 ) ;\
361 PXOR ( MM7, MM3 ) /* unsigned -> signed */ ;\
362 PXOR ( MM7, MM4 ) /* unsigned -> signed */ ;\
387 MOVQ ( REGIND(ESP), MM7 ) ;\
393 GMB_MULT_GSR( MM1, MM2, MM4, MM5, MM7 ) ;\
|
| D | 3dnow_xform3.S | 170 PXOR ( MM7, MM7 ) /* 0 | 0 */
174 PFSUB ( MM5, MM7 ) /* | -x2 */
188 MOVD ( MM7, REGOFF(-4, EDX) ) /* write r3 */
232 MOVD ( REGOFF(8, ECX), MM7 ) /* | m2 */
233 PUNPCKLDQ ( REGOFF(24, ECX), MM7 ) /* m6 | m2 */
265 PFMUL ( MM7, MM0 ) /* x1*m6 | x0*m2 */
|
| /external/llvm/test/CodeGen/X86/ |
| D | ipra-reg-usage.ll | 6 …P2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6 MM7 R11 ST0 ST1 ST2 ST3…
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86Instr3DNow.td | 77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| D | X86InstrMMX.td | 155 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| D | X86RegisterInfo.td | 199 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86Instr3DNow.td | 77 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| D | X86InstrMMX.td | 152 Defs = [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 216 ENTRY(MM7)
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 214 ENTRY(MM7)
|
| /external/llvm-project/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 213 ENTRY(MM7)
|
| /external/capstone/arch/X86/ |
| D | X86DisassemblerDecoder.h | 224 ENTRY(MM7)
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 132 {codeview::RegisterId::MM7, X86::MM7}, in initLLVMToSEHAndCVRegMapping()
|
| D | X86InstComments.cpp | 209 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
|
| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 130 {codeview::RegisterId::MM7, X86::MM7}, in initLLVMToSEHAndCVRegMapping()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 146 MM7 = 126,
1246 { X86::MM7 },
2106 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
2763 { 48U, X86::MM7 },
2824 { 36U, X86::MM7 },
2869 { 36U, X86::MM7 },
2930 { 48U, X86::MM7 },
2991 { 36U, X86::MM7 },
3036 { 36U, X86::MM7 },
3082 { X86::MM7, 48U },
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 149 CV_REGISTER(MM7, 153)
|
| /external/llvm-project/llvm/include/llvm/DebugInfo/CodeView/ |
| D | CodeViewRegisters.def | 150 CV_REGISTER(MM7, 153)
|
| /external/llvm/docs/TableGen/ |
| D | index.rst | 65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
|
| D | LangIntro.rst | 543 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| /external/llvm-project/llvm/docs/TableGen/ |
| D | index.rst | 68 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
|
| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 159 def MM7 : X86Reg<"mm7", 7>, DwarfRegNum<[48, 36, 36]>;
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 168 if (X86::MM0 <= RegNo && RegNo <= X86::MM7) in getVectorRegSize()
|