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Searched refs:MO2 (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp82 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
95 printRegName(O, MO2.getReg()); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
346 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
358 printRegName(O, MO2.getReg()); in printSORegRegOperand()
366 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
371 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp102 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
115 printRegName(O, MO2.getReg()); in printInst()
125 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
385 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
397 printRegName(O, MO2.getReg()); in printSORegRegOperand()
405 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
410 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
[all …]
DARMMCCodeEmitter.cpp937 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
939 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1255 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1258 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1259 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1260 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1349 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1364 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1512 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1513 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp102 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
115 printRegName(O, MO2.getReg()); in printInst()
125 const MCOperand &MO2 = MI->getOperand(2); in printInst() local
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
385 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegRegOperand() local
397 printRegName(O, MO2.getReg()); in printSORegRegOperand()
405 const MCOperand &MO2 = MI->getOperand(OpNum + 1); in printSORegImmOperand() local
410 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()), in printSORegImmOperand()
[all …]
DARMMCCodeEmitter.cpp929 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
931 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1247 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1250 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1251 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1252 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1341 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1356 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1504 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1505 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
[all …]
/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp56 const MachineOperand &MO2);
61 const MachineOperand &MO2);
182 const MachineOperand &MO2) { in isIdenticalOp() argument
183 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
196 const MachineOperand &MO2) { in isSimilarDispOp() argument
197 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
199 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
200 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
201 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
202 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp68 const MachineOperand &MO2);
73 const MachineOperand &MO2);
202 const MachineOperand &MO2) { in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
215 const MachineOperand &MO2) { in isSimilarDispOp() argument
216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
218 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
221 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp68 const MachineOperand &MO2);
73 const MachineOperand &MO2);
202 const MachineOperand &MO2) { in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
215 const MachineOperand &MO2) { in isSimilarDispOp() argument
216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
218 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
221 (MO1.isSymbol() && MO2.isSymbol() && in isSimilarDispOp()
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/external/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430MCCodeEmitter.cpp127 const MCOperand &MO2 = MI.getOperand(Op + 1); in getMemOpValue() local
128 if (MO2.isImm()) { in getMemOpValue()
130 return ((unsigned)MO2.getImm() << 4) | Reg; in getMemOpValue()
133 assert(MO2.isExpr() && "Expr operand expected"); in getMemOpValue()
146 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(), in getMemOpValue()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430MCCodeEmitter.cpp127 const MCOperand &MO2 = MI.getOperand(Op + 1); in getMemOpValue() local
128 if (MO2.isImm()) { in getMemOpValue()
130 return ((unsigned)MO2.getImm() << 4) | Reg; in getMemOpValue()
133 assert(MO2.isExpr() && "Expr operand expected"); in getMemOpValue()
146 Fixups.push_back(MCFixup::create(Offset, MO2.getExpr(), in getMemOpValue()
/external/capstone/arch/ARM/
DARMInstPrinter.c478 MCOperand *MO2 = MCInst_getOperand(MI, 2); in ARM_printInst() local
525 printRegName(MI->csh, O, MCOperand_getReg(MO2)); in ARM_printInst()
528 …->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO2); in ARM_printInst()
541 MCOperand *MO2 = MCInst_getOperand(MI, 2); in ARM_printInst() local
543 opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)); in ARM_printInst()
591 tmp = translateShiftImm(getSORegOffset((unsigned int)MCOperand_getImm(MO2))); in ARM_printInst()
680 MCOperand *MO2 = MCInst_getOperand(MI, 4); in ARM_printInst() local
681 if ((getAM2Op((unsigned int)MCOperand_getImm(MO2)) == ARM_AM_add && in ARM_printInst()
682 getAM2Offset((unsigned int)MCOperand_getImm(MO2)) == 4) || in ARM_printInst()
683 MCOperand_getImm(MO2) == 4) { in ARM_printInst()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp864 const MCOperand &MO2 = MI.getOperand(OpIdx + 1); in getThumbAddrModeRegRegOpValue() local
866 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
1071 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getLdStSORegOpValue() local
1074 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()); in getLdStSORegOpValue()
1075 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add; in getLdStSORegOpValue()
1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1165 const MCOperand &MO2 = MI.getOperand(OpIdx+2); in getAddrMode3OpValue() local
1180 unsigned Imm = MO2.getImm(); in getAddrMode3OpValue()
1328 const MCOperand &MO2 = MI.getOperand(OpIdx + 2); in getSORegRegOpValue() local
1329 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
[all …]
/external/llvm-project/llvm/unittests/CodeGen/
DMachineOperandTest.cpp405 MachineOperand MO2 = MachineOperand::CreateES(SymName2); in TEST() local
407 ASSERT_EQ(hash_value(MO1), hash_value(MO2)); in TEST()
408 ASSERT_TRUE(MO1.isIdenticalTo(MO2)); in TEST()
/external/llvm/lib/CodeGen/
DScheduleDAGInstrs.cpp706 for (const MachineOperand &MO2 : MI->operands()) { in collectVRegUses() local
707 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1224 MCOperand &MO2) { in makeCombineInst() argument
1229 TmpInst.addOperand(MO2); in makeCombineInst()
1585 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1587 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1592 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1606 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1607 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1461 MCOperand &MO1, MCOperand &MO2) { in makeCombineInst() argument
1466 TmpInst.addOperand(MO2); in makeCombineInst()
1809 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1811 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1816 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1830 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1831 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1235 MCOperand &MO2) { in makeCombineInst() argument
1240 TmpInst.addOperand(MO2); in makeCombineInst()
1597 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1599 if (MO2.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1604 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1618 MCOperand &MO2 = Inst.getOperand(2); in processInstruction() local
1619 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp402 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
403 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp952 MachineOperand &MO2 = Cond[2]; in reverseBranchCondition() local
953 switch (MO2.getReg()) { in reverseBranchCondition()
955 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
958 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp952 MachineOperand &MO2 = Cond[2]; in reverseBranchCondition() local
953 switch (MO2.getReg()) { in reverseBranchCondition()
955 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
958 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp964 MachineOperand &MO2 = Cond[2]; in ReverseBranchCondition() local
965 switch (MO2.getReg()) { in ReverseBranchCondition()
967 MO2.setReg(AMDGPU::PRED_SEL_ONE); in ReverseBranchCondition()
970 MO2.setReg(AMDGPU::PRED_SEL_ZERO); in ReverseBranchCondition()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp452 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
453 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp452 MCOperand &MO2 = MappedInst.getOperand(2); in HexagonProcessInstruction() local
453 MCExpr const *Expr = MO2.getExpr(); in HexagonProcessInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineScheduler.cpp948 for (const MachineOperand &MO2 : MI.operands()) { in collectVRegUses() local
949 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()
/external/llvm-project/llvm/lib/CodeGen/
DMachineScheduler.cpp965 for (const MachineOperand &MO2 : MI.operands()) { in collectVRegUses() local
966 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) { in collectVRegUses()

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